Cerpin has quit [Remote host closed the connection]
Cerpin has joined #yosys
Cerpin has quit [Remote host closed the connection]
Cerpin has joined #yosys
Cerpin has quit [Read error: Connection reset by peer]
Cerpin has joined #yosys
rohitksingh_work has joined #yosys
<emeb_mac>
question on nextpnr-ice40: trying to use an instance of SB_PLL40_CORE with reference clock originating on-chip in the 48MHz HF osc. Yosys runs OK but nextpnr gives me an error: ERROR: PLL 'pll_inst' couldn't be placed anywhere, no suitable BEL found.
<emeb_mac>
This is on a up5k design with clock originating on-chip (not coming from an IO pad)
<emeb_mac>
(reference clock that is)
emeb_mac has quit [Ping timeout: 272 seconds]
proteusguy has joined #yosys
m4ssi has joined #yosys
pie__ has joined #yosys
leviathanch has joined #yosys
mwk has quit [Ping timeout: 268 seconds]
<corecode>
hm, why can't it place it
<tnt>
I made a test case and it works for me.
<tnt>
So I'm waiting from him to come back and post a snippet of what he's doing ...
<corecode>
yea
<daveshah>
maybe pin 35 is being used and blocking the pll
<tnt>
Oh yeah, right, that's probably it.
<corecode>
say what?
<daveshah>
certain pins can only be used as outputs when the pll is used
<tnt>
PLL input path is shared with the IO input path of the IO tile it's in.
<corecode>
so the pll is a padin, not a gbufin?
<daveshah>
yes
<corecode>
already forgot again
<corecode>
that seems dumb
<daveshah>
likewise PLLOUTCORE{A,B} use the D_IN_0s of the IO tile they are in
leviathanch has quit [Read error: Connection reset by peer]
citypw has joined #yosys
mwk has joined #yosys
flaviusb has quit [Ping timeout: 255 seconds]
rohitksingh_work has quit [Read error: Connection reset by peer]
flaviusb has joined #yosys
develonepi3 has quit [Remote host closed the connection]
vmedea has joined #yosys
rohitksingh has joined #yosys
emeb has joined #yosys
rohitksingh has quit [Ping timeout: 250 seconds]
rohitksingh has joined #yosys
leviathanch has joined #yosys
rohitksingh has quit [Ping timeout: 272 seconds]
flaviusb has quit [Ping timeout: 240 seconds]
leviathanch has quit [Remote host closed the connection]
flaviusb has joined #yosys
<emeb>
Just read the channel log - saw the advice on pin 35 vs PLL. Thanks for that - I'll check if moving I/O around in the .pcf helps.
<emeb>
Yes - I did have pin 35 defined as input and freeing it up allowed the PLL to be placed.
<emeb>
Unfortunately, I'm using a upduino V1 for this test and the mistakes in the board design WRT the PLL supply seem to be preventing it from working.
<emeb>
Well, I've got my own boards waiting to be built with proper PLL supply ckts. Will have to wait for those.
develonepi3 has joined #yosys
rohitksingh has joined #yosys
<tnt>
emeb: if you have a bit of wire, you can 'fix' it :p
m4ssi has quit [Quit: Leaving]
<emeb>
tnt: yeah, I could. but, #effort. :)
<emeb>
lol - routed the PLL clock output to a pin and put it on the 'scope.
<emeb>
such jitter!
<tnt>
oh really ? I guess it's not locked right ?
<MoeIcenowy>
I think the internal OSC itself is weird
<MoeIcenowy>
upduino v1... weird board
<MoeIcenowy>
it's even worse than designing one by yourself
<MoeIcenowy>
(recently I purchased a UPduino before I started my own UP5K board, and received it after finished the sample
<MoeIcenowy>
(then I regretted to purchase the UPduino
<MoeIcenowy>
although it's v2
<emeb>
I'm trying to make a 16 MHz clock from the on-board 48MHz with the PLL. The actual output freq is about 1.2MHz and very wiggly.
<MoeIcenowy>
emeb: why not use DIV?
<MoeIcenowy>
16 = 48 / 3
<MoeIcenowy>
add #(.CLKHF_DIV("0b10")) to the SB_HFOSC
<tnt>
MoeIcenowy: I think div only does 48 24 12 6 ...
<emeb>
correct
<emeb>
16 is not an option
<emeb>
I actually have a /3 circuit stubbed in for now
<corecode>
that hfosc is probably not very good
<emeb>
but only 33% duty cycle, so I wanted to try the PLL
<corecode>
looked jittery to me
<MoeIcenowy>
oh forgot it
<MoeIcenowy>
how to mod my brain to have an ECC memory?
<corecode>
more system 2
<corecode>
operate as if you are likely to make mistakes
<emeb>
averaging on for smoother skirts - about 30dB down @ 100kHz offset
<emeb>
correction - 200kHz offset
<MoeIcenowy>
if I have an oscilloscape I will try to do the experiment on UPduino2 and iCECream v1
<tnt>
iCECream ? didn't know that one.
<MoeIcenowy>
it's my own board ;-)
<MoeIcenowy>
only 3 fully-installed ones exist on the world ;-)
<tnt>
Ah I see :)
<MoeIcenowy>
in fact it's available on my github
pie__ has quit [Remote host closed the connection]
pie__ has joined #yosys
<ylamarre>
This whole project should just be renamed icepun or icywhatyoudid....
* shapr
snickers
<ylamarre>
You shouldn't give this proposition the cold shoulder...
<ylamarre>
Or are you just having cold feet?
<shapr>
The name symbioyosys got a laugh from me first time I saw it.
<ylamarre>
Ok, symbioyosys is actually pretty good.
<sorear>
did you misspell symbiyosys or are you making a deeper joke I don't get
<ylamarre>
I followed shapr's spelling...
<shapr>
sorear: I got the spelling wrong, sorry
rohitksingh has quit [Remote host closed the connection]
brandonz has quit [Ping timeout: 240 seconds]
brandonz has joined #yosys
<sxpert>
it's a nice pun on symbiosis, obviously
maikmerten has joined #yosys
<elms>
Looking for some details on iCE40 IE/REN and ColBufCtrl. Is this the best place to ask (I know it's more icestorm than yosys)? If there is a document with more details I can start there.