clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<emeb_mac> tnt: have you tried to use SB_SPI in up5k before? when I try I get the following error in nextpnr: ERROR: cell type 'SB_SPI' is unsupported (instantiated as 'uut.usysbus.spiInst0')
<emeb_mac> this despite the fact that nextpnr reports SB_SPI as one of the available cells in the utilization report.
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<tnt> emeb_mac: mmm, indeed looks like nextpnr is lacking support for it :/
<emeb_mac> tnt: weird
<emeb_mac> esp. since it's listed in the utilization report
<tnt> The usage report is based on the chipdb, but you still need some code to support placing it. I'll see if I can add support for it.
<emeb_mac> :)
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<Forty-Bot> is there a way to only preprocess?
<Forty-Bot> ...and I have discovered -ppdump
<cr1901_modern> TIL
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<davos> hey, I am using an ice40 ultra plus, trying to get the SPI IP block to work. I read through notes about ultra plus on the icestorm and it says there are 4 SPI_ENABLE_* signals. Wondering how to enable the SPI IP block in verilog? Is there an example anywhere for setting that type of signal?
<tpb> Title: ice40: Add support for SB_I2C and SB_SPI · smunaut/nextpnr@716b371 · GitHub (at github.com)
<tnt> (not hw proven yet ... I wrote that like 1h ago)
<emeb> davos: I'm trying tnt's patch for nextpnr right now - it seems to build OK but I need to test it further.
<emeb> here's how I instantiated it -> https://pastebin.com/HWPTaQ7b
<tpb> Title: // system_bus.v - wrapper for wishbone master and system bus IP cores // 03-21- - Pastebin.com (at pastebin.com)
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