clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach_> corecode : do you think yosys-smtbmc is able to do NoC deadlock verification ?
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<shorne> Hello, I am trying to synthesize mor1kx (an openrisc core) with yosys. I'm using the today's git version of yosys for the first time
<shorne> just trying to run something like : yosys -f verilog -o synth.v -S mor1kx_dmmu.v mor1kx_true_dpram_sclk.v mor1kx_immu.v ....
<shorne> after MEMEMORY_MAP phase I just get "Killed"
<shorne> and it exits
<shorne> something I am doing wrong?
<tnt> Does 'dmesg' say anything ?
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<daveshah> shorne: is it possible there are any large (e.g. tens to hundreds of MB) RAMs in there?
<tnt> I would more suspect a RAM that ends up not being mapped to ... RAM.
<daveshah> No RAMs will be mapped to RAM with -S which is generic logic synthesis
<shorne> ok, maybe I am missing ram mapping
<shorne> there might be around 1 MB or ram
<shorne> We have caches and a ton of registers
<shorne> but not that much
<shorne> Running again
<shorne> tnt: right its the oom killer
<shorne> Out of memory: Kill process 21146 (yosys) score 614 or sacrifice child
<tnt> 1 MB done in FF is ... a lot of FF and muxes and ... :p
<shorne> ok, it worked after doing: yosys -f verilog -o synth.v -p memory -p opt -S mor1kx_dmmu.v ...
<shorne> I was thinking the MEMORY_MAP was doing the memory conversions
<shorne> Sorry, first time using yosys
<shorne> recently I have just been using iverilog/verilator ... not synthesizing anything :)
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<corecode> promach: how would you detect a deadlock?
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<corecode> promach: what did you implement for your NoC so far?
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<develonepi3> andrewrk, updated zig ver c4887d7f. This is the cmd that I used to get zigmain.o zig build-obj -isystem ../../include/ -isystem /usr/lib/arm-none-eabi/include -isystem /usr/lib/arm-none-eabi -target armv7-freestanding-gnueabihf zigmain.zig.
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<promach_> corecode : if I use Spidergon, then I am afraid that I cannot avoid deadlock. I am not sure if I could combine Spidergon with turn-restriction routing
<promach_> I am not sure if I even want to detect
<promach_> when I could avoid/eliminate deadlock entirely
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<corecode> why would you get a deadlock?
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<FL4SHK> Does yosys have a VHDL frontend?
<FL4SHK> also, regarding formal verification with yosys, is there any way to do so with VHDL?
<FL4SHK> My guess and possibly correct "knowledge" is that neither of these are available.
<FL4SHK> I thought I'd ask anyway, though.
<tnt> There is a commercial 'plugin' I think.
<daveshah> FL4SHK: There are some experimental projects to add VHDL frontends to Yosys, ime the best option is vhdl2vl
<daveshah> The commercial frontend is Verific. This does support formal verification, at least asserts (not sure about assumes)
<daveshah> If your purposes are research/personal/academic a free license might be available
<tpb> Title: Research Partner License Program (SERP) Symbiotic EDA (at www.symbioticeda.com)
<FL4SHK> vhd2vl's existence actually surprises me
<FL4SHK> wait
<FL4SHK> doesn't support pcakages, structures, or functions?
<FL4SHK> without those features, I have no need to use VHDL
<tnt> :)
<daveshah> No, vhdl2vl pretty much supports the verilog feature set only
<FL4SHK> guess I'll continue with my compiler project then, heh.
<FL4SHK> I'm not working on a VHDL compiler, but rather a compiler for a custom HDL
<FL4SHK> it'll be spitting out Verilog-2001
<FL4SHK> the fact that it carries over comments is intriguing
<FL4SHK> *the fact that vhd2vl
<FL4SHK> I may or may not want to do so myself...
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