clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<develonepi3> Hello all: I have code for my catboard sdram design.
<develonepi3> The lines below work when I use arachne-pnr in h/w not simulation.
<develonepi3> assign io_ram_data = (ram_drive_data) ? o_ram_data : 16'bzzzz_zzzz_zzzz_zzzz;
<develonepi3> always @(posedge s_clk)
<develonepi3> r_ram_data_ext_clk <= io_ram_data;
<develonepi3> always @(posedge s_clk)
<develonepi3> i_ram_data <= r_ram_data_ext_clk;
<develonepi3> How would you write this for sb-io? I need to start using nextpnr
<develonepi3> Hello all: My design is similar to zipcpu icozip for the icoboard.
<develonepi3> ppio #(.W(16))
<develonepi3> sramioi(o_ram_we_n, io_ram_data, o_ram_data, i_ram_data);
<develonepi3> This does not work for me.
<develonepi3> ppio #(.W(16))
<develonepi3> sdramioi(o_ram_we_n, io_ram_data, o_ram_data, i_ram_data);
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<daveshah> develonepi3: see this SB_IO example
<tpb> Title: picorv32/hx8kdemo.v at master · cliffordwolf/picorv32 · GitHub (at github.com)
<daveshah> Can you explain your second question a bit more clearly? What do you mean does not work?
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<develonepi3> daveshah: I am running several C programs cputest, hello, and jpeg which does a lifting step dwt using zipcpu on the catboard that require the SDRAM to provide stoarage. The upper 16 bits of 32 bit board work but the lower 16 bits can not be written.
<daveshah> develonepi3: What SDRAM controller are you using? How is it connected?
<daveshah> I'm not sure what you mean by 32 bit board, the CAT board appears to only have a 16 bit SDRAM on it
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<develonepi3> devshah: you can store 2 16 words is what zipcpu uses data is transferred from RPi to sdram using 8bit parallel port.see https://github.com/develone/catzip/blob/master/doc/zipcpu.pdf
<tpb> Title: catzip/zipcpu.pdf at master · develone/catzip · GitHub (at github.com)
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