<corecode>
emeb: actually i just want to try my forth cpu on an fpga
<corecode>
but icecube2 fails to place it
<corecode>
so now i'm - under protest - porting icestorm to the fpga i'm using
voxadam has quit [Ping timeout: 245 seconds]
seldridge has quit [Ping timeout: 245 seconds]
voxadam has joined #yosys
gsi__ has joined #yosys
gsi_ has quit [Ping timeout: 257 seconds]
citypw has quit [Quit: Leaving]
<emeb>
corecode: interesting problem
<emeb>
which FPGA are you using?
emeb has quit [Quit: Leaving.]
rohitksingh has joined #yosys
Marex_ has joined #yosys
awordnot has quit [Ping timeout: 246 seconds]
Marex has quit [Ping timeout: 246 seconds]
svenn has quit [Ping timeout: 246 seconds]
Kooda has quit [Ping timeout: 246 seconds]
svenn has joined #yosys
awordnot has joined #yosys
FL4SHK has quit [Ping timeout: 246 seconds]
awordnot has quit [Ping timeout: 240 seconds]
awordnot has joined #yosys
FL4SHK has joined #yosys
jevinskie has joined #yosys
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh has joined #yosys
leviathanch has joined #yosys
emeb_mac has quit [Ping timeout: 240 seconds]
rohitksingh has quit [Ping timeout: 246 seconds]
jevinskie has quit [Read error: Connection reset by peer]
jevinski_ has joined #yosys
rohitksingh has joined #yosys
_whitelogger has joined #yosys
rohitksingh has quit [Ping timeout: 246 seconds]
m_w has quit [Ping timeout: 246 seconds]
<corecode>
the ice5lp1k
xdeller__ has quit [Read error: Connection reset by peer]
xdeller__ has joined #yosys
<sxpert>
daveshah: getting some messages from yosys when compiling about "assert" being used while read_verilog is not called with -sv on ecp5/cells_sim.v:41[1-4]
maikmerten has joined #yosys
mrec has joined #yosys
<mrec>
I wonder is Clifford here?
<daveshah>
sxpert: hmm, perhaps an ifdef is needed
<daveshah>
mrec: no, not usually
<mrec>
some of his slides seem to be wrong ice40up5k doesn't have 128kbit bram, it's supposed to be 120kbit
<mrec>
30*4k
<daveshah>
Indeed that is correct, I'll let him know
<mrec>
well the specs are also wrong at the bottom of the pdf
* sxpert
would like an ECP-5 100k with 8Mbit of bram ;)
<mrec>
I'm happy with the ice40up for small items, the crappy linux spi implementation needs a lot cache
Marex_ is now known as Marex
<daveshah>
SPRAM would probably make sense
<mrec>
hmm is there anything better/faster/free available for simulating ice40 (mixed vhdl/verilog) designs than ActiveHDL?
<daveshah>
Mixed HDL, probably not
<mrec>
it takes quite a few seconds to simulate 10 milliseconds
<mrec>
more like a minute+
<daveshah>
Verilator will be much faster, but is Verilog only
<daveshah>
it also might not support the vendor verilog models, because it doesn't implement the full event model, but it should work with the Yosys ones
<corecode>
i have no idea whether i am 10% or 90% done with the ul port
<daveshah>
If you want to create a PR or stick the repo somewhere I'm happy to take a look
<corecode>
thanks
<daveshah>
If you can get meaningful output from icebox_vlog for a few small designs from icecube (unpacked with iceunpack) then that's a good first step
* sxpert
is happy, his decoder and alu can both be stalled at the same time by the bus controller
<sxpert>
for example, when said bus controller will have to go fetch some dram data