clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach_> ZipCPU: Which part of the code you still do not understand ? I will make them clearer
<corecode> daveshah: do you know how the colbuf_db is made?
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<corecode> i made + ran a colbuf_io*.sh, but i don't know what i am looking for in the output
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<corecode> yea i need some assistance figuring out these last bits
<corecode> unclear where they come from and what the order needs to be
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<daveshah> corecode: colbuf_logic is probably the most important script.
<daveshah> You should get four numbers per line
<daveshah> in each case, x and y of the column buffer and x and y of the global user
<daveshah> Chances are that x will be the same for both
<daveshah> So then in icebox.py you are creating a mapping from global user location (the second pair of numbers) to colbuf location (the first pair)
<daveshah> I think there is also a script to visualise this as an svg
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<corecode> the script falls on its face tho, because it icebox to already know where the colbuf is
<corecode> i think
<daveshah> No, it only needs to know what the colbuf bits are
<daveshah> They should be the same across devices
<daveshah> That's different to the tile locations where colbufs are
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<promach> ZipCPU: Which part of the code you still do not understand ? I will make them clearer. I need your comment because that would make the code more user-readable and user-friendly
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<sxpert> there is $display, is there a $waitkey function ?
<ZipCPU> When using Verilator, it's not that hard to build. As I recall, that was one of my tutorial lessons ;)
<sxpert> ZipCPU: so I rewrote it all again ;)
<sxpert> yosys finds 669 cells and next-pnr finds 316, is that supposed to be normal ?
<sxpert> (after all there's 2 lut per cell, so that seems plausible)
<ZipCPU> sxpert: Yes, that's normal
<sxpert> ok
<sxpert> so far, I manage to execute the first 8 instructions of the rom ;)
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<somlo> daveshah: after prjtrellis commit 72418c7 there's still an explicit basecfg reference in examples/picorv32_versa5g/Makefile; do you want to fix that separately, or should I include it in the rebased PR #59 (where I'm adding "TRELLIS=/usr/share/trellis" to get rid of the remaining openocd relative paths?
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<tnt> corecode: mm, what are you working on if you don't mind me asking ?
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<corecode> trying to get ice5lp support in icestorm
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<tnt> corecode: ah, nice ! I thought that might have been it from the questions, but wanted to double-check :p
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<daveshah> somlo: feel free to add to your PR
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<somlo> daveshah: done
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<tpb> Title: Sipeed TANG PriMER FPGA Development Board - Seeed Studio (at www.seeedstudio.com)
<daveshah> micko is working on them: https://github.com/mmicko/prjtang
<tpb> Title: GitHub - mmicko/prjtang: Documenting the Anlogic FPGA bit-stream format. (at github.com)
<keesj> thanks daveshah I just found it !
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