<tpb>
Title: //`define USE_BRAM `ifdef USE_BRAM // put code in a pre-loaded block ram - Pastebin.com (at pastebin.com)
<emeb>
either of those two works in iverilog, but only the case() works in hardware
<daveshah>
Are you waiting the requisite ~10µs after startup?
<emeb>
Not explicitly.
<daveshah>
The iCE40 BRAM isn't properly initialised at boot
<daveshah>
you have to wait about 10µs or so for it to work
<emeb>
OK - I've got a 2us reset generator. Can try extending that.
<daveshah>
might be worth trying
<emeb>
Thanks for the heads-up. That's a very "interesting" detail.
<emeb>
daveshah: OK - that seems to have fixed it. Many thanks.
<sxpert>
daveshah: ok, rewrote lots of my code last night
<sxpert>
I am at the point where I have most of my imbricated ifs at 3 levels
<sxpert>
is that too much ?
<somlo>
daveshah: mind rebasing nextpnr PR#219 (it now clashes with commit 565d5ee, and I don't feel qualified to decide how to resolve the conflict myself :)
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<daveshah>
somlo: done
<daveshah>
sxpert: not sure, depends if it meets timing at the end of the day]
<somlo>
daveshah: thanks!
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<emeb>
feeling kinda dumb for not knowing about that 10us startup delay on ice40 BRAM. But quick scanning thru Lattice docs for BRAM and config/startup didn't reveal any obvious documentation for it. Anyone have a reference, or did Lattice just blow it off?
<tpb>
Title: Block ram reads within ~36 cycles of device reset always return 0, but only on the first reset after device reconfiguration. · Issue #76 · cliffordwolf/icestorm · GitHub (at github.com)
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<maikmerten>
errata are fun. Undocumented errata are even more fun
<maikmerten>
(depending on your definition of fun)
<emeb>
"teachable moments"
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<ZipCPU>
Ok ... my proof is running. Anyone want to chat about what they're up to?
<ZipCPU>
:D
<chaseemory>
im trying to get the ethernet port on my nexys_video working :D
<tpb>
Title: GitHub - ZipCPU/videozip: A ZipCPU SoC for the Nexys Video board supporting video functionality (at github.com)
<ZipCPU>
chaseemory: Is that your own repository, or someone elses?
<chaseemory>
someone elses
<chaseemory>
I hadnt ever used axi either, so i was reading a few of your articles on it this morning, thinking thats where my hangups were
<ZipCPU>
Heh -- that's today's task, creating a set of formal properties to verify an AXI component
<ZipCPU>
Does his controller run with AXI?
* ZipCPU
looks for the spec/documentation
<chaseemory>
yeah it uses AXI-stream throughout
<ZipCPU>
Ok, got it
<ZipCPU>
I used my own streaming protocol when I needed one
<ZipCPU>
I've never tried to verify anything with AXI stream in it so far ... it just looked too easy (Of course, I've never used AXI stream, so I could be pretty wrong there too ...)
<ZipCPU>
chasemory: What speed are you trying to run the port at?
<chaseemory>
gigabit, that repo supports gig or 10gig, not that ill be using all that bandwidth
<ZipCPU>
I ask only because at the end of the day, I was getting a weird hw/sim mismatch. My guess was that the 125MHz clock from the PHY wasn't running at a constant speed. (I was trying to use the receive clock for transmit as well.)
<chaseemory>
i know axi says all the lines need to be registered, but im running all of mine combinatorialy, but only based off the current state, so i thought itd be ok
<ZipCPU>
Ok, well ... is it okay?
<sxpert>
I worked on what I learned yesterday. in particular, reducing the level of if/case imbrications
<ZipCPU>
sxpert: Still on the fence with formal methods?
* ZipCPU
looks over his proof ... it's still running
<sxpert>
well, I started reading, but still haven't fully understood the thing
<ZipCPU>
Have you found any of the examples of the counters?
<tpb>
Title: My first experience with Formal Methods (at zipcpu.com)
<sxpert>
(took a while)
<ZipCPU>
There's a better interface to the tools than that article presents
<ZipCPU>
So, when writing a CPU, there tend to be lots of redundancy within the FFs of a design
<ZipCPU>
Hmm ... let me start over
<ZipCPU>
Within a CPU, you have very specific requirements you need to meet. Perhaps the two biggest are 1) the peripheral/memory interface, and 2) that your various instructions do as you expect
<sxpert>
I'll keep 1 for later
<ZipCPU>
The neat thing about 1, though, is that once you do it ... it applies everywhere throughout your design--everywhere you (re)use that basic interface
<sxpert>
I'm currently working on decoding all those instructions to something the thing can use
<ZipCPU>
Yesh, decoders tend to be ugly
<ZipCPU>
Easy to verify, but ugly to code
<sxpert>
well, there's a method to the madness ;)
<sxpert>
in particular with that device, everything more or less goes through the ALU
<ZipCPU>
Risc-V's are even uglier to decode than ... a lot of the other things I've seen
<ZipCPU>
I had a challenge to prove that I had the right registers going into my ALU. Your CPU as I recall is much simpler
<ZipCPU>
I was struggling to deal with interrupts, memory wait states, divide and multiply wait states, etc
<sxpert>
currently, I'm decoding most of it to dest, op, src1, src2, start_nibble, end_nibble
<ZipCPU>
Do all of your instructions fit within one word, or are they multi-byte instruction strings?
<sxpert>
they can be up to 21 4 bits nibble
* ZipCPU
looks over his proof ... it's still going after step 35, but now up to 30 minutes
<ZipCPU>
Let's see ... that's up to nearly 10-bytes long?
<sxpert>
10.5
<ZipCPU>
That's ugly
<ZipCPU>
Can you at least depend upon a one clock delay from memory when attempting to read instructions?
<sxpert>
longest opcode is LA (Load A), 8082n[n-nibbles]
<ZipCPU>
Load address ... how big is your address space?
<sxpert>
nah, load register A, addresses are 5 nibbles
<sxpert>
registers are 64 bits
<sxpert>
except memory addressing registers that are 20 bits
<ZipCPU>
How many registers?
<sxpert>
A, B, C, D are the main ones, then you have R[0-4] that you can only save into from A or C, then 2 pointers D0 and D1, and some ancillary stuff
<ZipCPU>
So you have several special purpose registers then?
<sxpert>
yeah, there's a 4 bits P register to point at a particular nibble in one of the others
<sxpert>
some status bits, and an 8 level return stack
<ZipCPU>
Only 8 stack entries?
<sxpert>
yeah
<ZipCPU>
20'bits of memory? Or just a 20'bit address space?
<sxpert>
20 bits address space, you can configure ram modules to be anywhere in the address space, and move them around as needed
<ZipCPU>
And I think you said that the RAM was guaranteed to respond in one cycle, right?
<sxpert>
well, there's a bus controller that fakes it if required
<sxpert>
(it can stall the cpu if needs be)
<ZipCPU>
Really? What type of bus?
<ZipCPU>
Custom, or well-known?
<sxpert>
between the cpu and the external memory controller is a 4 bits bus, through which things like adresses are sent one nibble at a time
<ZipCPU>
A 64-bit CPU, but with only 4'bits of data bus?
<tpb>
Title: HP Saturn - Wikipedia (at en.wikipedia.org)
<sxpert>
that article says it all ;)
<sxpert>
so the HP thinkjet
<ZipCPU>
That article has a *LOT* of links and tables
<sxpert>
there's a "chipsets and applications" paragraph
<ZipCPU>
Not sure I'd call that a "paragraph" ;)
<sxpert>
well, table then ;)
<ZipCPU>
Let's see ... I bought my first HP calculator in ... was in '95?
<ZipCPU>
(It wasn't a graphing calculator ... ;(
<sxpert>
then that's what's in there ;)
<sxpert>
which one was it ?
<ZipCPU>
Looking for it now ...
<ZipCPU>
The 22S looks familiar
<ZipCPU>
I might have to head upstairs and find out ...
<ZipCPU>
Here it is: the HP-20S
<ZipCPU>
I bought it during a final exam, when I realized afterwards that I needed a calculator for the exam
<sxpert>
saturn it is ;)
<sxpert>
1LU7, bert ;)
<ZipCPU>
I thought I was buying an RPN calculator. The 20S isn't an RPN calculator. It took me a bit before I was productive with it--all during my final exam
<sxpert>
heh
<sxpert>
and there's that business series that one needs to be careful about ;)
<ZipCPU>
Sounds like you are working on an amazing project. Thanks for sharing!
<ZipCPU>
Why so?
<sxpert>
you mean, the business series ? well they don't do scientific maths ;)
<ZipCPU>
Heh, okay, yeah. I avoided that series
<ZipCPU>
The one I purchased could do a 3x3 matrix inverse ... but there was no way I would've figured out how to do that during that final exam
<sxpert>
heh
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