<maikmerten>
I certainly would not have assumed that one can somehow drive a ~147 MHz pixel clock through such a setup, without any attempt of termination etc.
<maikmerten>
so the signals signals go FPGA board -> extension board with SRAM and Pmod -> Pmod connector -> Pmod to ISP cable adapter -> ISP cable -> ISP cable to Pmod adapter -> Pmod connector -> non-inverting bus driver with resistor DAC
<sxpert>
works as long as your total wire lengh < 1m or so
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<maikmerten>
"<sxpert> works as long as your total wire lengh < 1m or so" -- that sounds like a very thumby rule of thumb ;-)
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<corecode>
hi
<corecode>
i guess in the end i do have to port icestorm to my ice5lp, because icecube's placer fails with my design
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<sxpert>
maikmerten: it is ;)
<sxpert>
can I use "=" for a result that I need in a calculation immediately in an "always @(posedge clk)" block ?
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<maikmerten>
sxpert, yes, I'm pretty sure I used that once
<maikmerten>
sxpert, ended up removing that, though, because verilator does *not* allow that
<maikmerten>
(iverilog is okay with that style, though)
<maikmerten>
okay, yes, used that a while back
<maikmerten>
always @(negedge clk) begin
<maikmerten>
...
<maikmerten>
if(!busy) state = nextstate; // assume new state NOW!
<maikmerten>
...
<maikmerten>
case(state)
<maikmerten>
etc. etc.
<maikmerten>
I *think* that style isn't overly recommended, though
<maikmerten>
for reasons more experienced Verilog developers can surely elaborate on ;-)
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<corecode>
sounds you're mixing combinational logic and flops?
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<sxpert>
ok so it's frowned upon
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<corecode>
i'm by no means an expert, but separating (complex) combinational logic and clocked logic (flops) helps understand the design better
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<lutsabound>
sxpert: why not use an @* block instead?
<somlo_>
daveshah: nextpnr PR #219 took me from 4:49:42 down to 0:17:26 (on a QEMU/KVM guest running on 2.4GHz Westmere hardware)
<somlo_>
haven't actually tried programming the board (it's at the office), so I'll do that tomorrow
<somlo_>
that's for the rocket-chip based blinky, to be precise
<somlo_>
oh, and that was before you force-pushed a newer version of the PR
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<sxpert>
ok, I did what I wanted with another solution ;-)
<sxpert>
(do some of the stuff in a previous phase...
<sxpert>
as in, an actual different clock phase
<sxpert>
(add moar registers)
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<sxpert>
looks like the instruction set I'm going for is too complicated, needs more thought, single cycle instructions are not really doable
<sxpert>
the original is probably microprogrammed
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<corecode>
sxpert: what are you making?
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<sxpert>
corecode: implementing a saturn architecture
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