clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> corecode : is your usb verilog code posted in github repo ?
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<jayaura> Hi, icebox_stat can list how many resources were used, but can some tool list whats the maximum available resources for the fpga the design was compiled for ?
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<corecode> promach: i don't have usb verilog code
<corecode> jayaura: you mean what the model has resources?
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<jayaura> corecode: yes, like giving the resource summary as "GBUF: 8 of 8" instead of "GBUF: 8" as I see now
<corecode> i guess you could modify the code
<jayaura> I mentioned gbuf figuratively.
<corecode> yes
<jayaura> i mean, the toolchain already know what resouces the fpga part contains. why not just say it :P
<corecode> because you didn't change the code yet
<jayaura> is that necessary? when I do a clean build, shouldnt it report the used and available resources?
<corecode> what do you mean by clean build
<daveshah> Both arachne-pnr and nextpnr will print both resource usage and total available during pnr
<jayaura> Ah sorry my mistake. I needed to look inbetween. I was looking at the end. arachne-pnr was only reporting span4 and span12 at the end, and not the LCs statistics, which was summarized right after placement
<promach> corecode : wait, I thought you said coded something on usb ?
<corecode> yes, for microcontrollers
<promach> so, the code is not in verilog ?
<promach> corecode
<corecode> no, it's code, not design
<promach> corecode : I do not get you
<promach> I remembered you said you coded something on usb ?
<promach> "it's code, not design" ??
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<corecode> yes, code
<corecode> for a microcontroller
<corecode> no hdl
<promach> c ?
<corecode> yes
<promach> I really do not want to deal with the usb linux driver c code
<promach> that is so ugly to debug if you really need to (which I think is bug-free)
<promach> corecode
<corecode> what is bug free?
<promach> free of bugs
<corecode> what is bug free
<promach> like receiving the wrong data from the usb protocol
<promach> which is impossible at all
<promach> given that usb had evolved so far
<corecode> what are you talking about
<promach> corecode
<promach> I am talking about libusb
<tpb> Title: Home · libusb/libusb Wiki · GitHub (at github.com)
<promach> c code is much more difficult to debug compared to verilog code
<promach> I might be wrong, but it is just personal experience
<promach> corecode
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<MoeIcenowy> icebox_vlog cannot deal with UP IP?
<MoeIcenowy> I tried to use it to generate a verilog for UPduino RGB blink sample
<MoeIcenowy> and I found no IP is generated
<daveshah> No, it can't
<MoeIcenowy> daveshah: I found that the verilog file of the sample defines LED pins as output
<MoeIcenowy> will the same be needed for yosys-nextpnr workflow?
<daveshah> No, just the driver primitive should be fine
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<MoeIcenowy> daveshah: a module without any input or output, but only IPs will not be "optimized"?
<corecode> wa?
<corecode> what kind of module would that be?
<corecode> no input or output
<MoeIcenowy> calls HFOSC
<MoeIcenowy> then RGBDRV
<corecode> calls?
<daveshah> Just double checked and keep isn't set on the RGB primitive, so it does need outputs actually
<daveshah> Adding `(* keep *)` here would change that if you wan it: https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v#L944
<tpb> Title: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at github.com)
<MoeIcenowy> but I think I will choose to use the oscillator on board with my own board ;-)
<MoeIcenowy> just borrow a bitstream from UPduino now to test
<MoeIcenowy> my iCE40UP5K-SG48I's arrived LCSC at Shenzhen today
<MoeIcenowy> and will ship to me tomorrow
<tnt> oh they have ice40s now ?
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<corecode> MoeIcenowy: where are you at?
<MoeIcenowy> tnt: no, it's digikey via LCSC ;-)
<MoeIcenowy> corecode: Guangzhou
<corecode> ah, close to sz
<corecode> or?
<MoeIcenowy> yes, close to sz
<MoeIcenowy> 1 hrs of high-speed train
<MoeIcenowy> s/hrs/hr/
<corecode> did you move there or were you born there?
<tnt> MoeIcenowy: oh they do that ? didn't know
<MoeIcenowy> corecode: moved here 9 yrs ago
<MoeIcenowy> tnt: only available at China
<corecode> do you like it?
<MoeIcenowy> strangely the components at Digikey via LCSC is (very) slightly cheaper than Digikey itself
<corecode> maybe special contract
<MoeIcenowy> for example, the price of iCE40UP5K-SG48I on Digikey itself is CNY 49
<MoeIcenowy> but on Digikey via LCSC it's 47
<MoeIcenowy> and Digikey itself requires one order must be at least CNY300
<MoeIcenowy> but Digikey via LCSC has no restriction
<MoeIcenowy> (yes, my order is only 5 iCE40UP5K-SG48I's, so it's less than 300
<corecode> i guess they pool orders
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<emeb> corecode: yay - got my old u4k breakout board blinking w/ your icestorm work. Thanks for getting that going.
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<corecode> cool
<emeb> corecode: do you have any idea how much effort it would be to add support for the LED driver core in u4k? Without that those three pins appear to be unusable.
<corecode> you can put ios on there
<corecode> but they are OD
<emeb> corecode: Ah ok - I'll give that a shot.
<emeb> OD is fine for driving LEDs - just don't get the current control I guess.
<corecode> yes
<emeb> seems to work fine. thx.
<corecode> cool
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<emeb> so I guess it's just that the proper hooks for those IP cores isn't in nextpnr at the moment?
<corecode> no
<corecode> the cores for the u4k are a bit different
<emeb> ah, so it would be necessary to RE them and add support to yosys too.
<corecode> yes, most of the work will be in icestorm
<emeb> ok, probably not really worth it just to save a few resistors. :)
<emeb> corecode: is there anyplace I can look to see exactly what features of u4k are unsupported, or is it just a "try and find out" problem?
<corecode> yes, look in icebox.py at the list of peripherals
<ylamarre> Documentation is in the code! :D
<ylamarre> Ah! :P
<corecode> the u4k ones are really short compared to the 5k
<corecode> so those can be reversed and/or confirmed
<emeb> corecode: thanks - I'll take a look.
<emeb> (don't know the ice* codebase well enough to know where everything is)
<daveshah> emeb: The resource utilisation print of nextpnr is also a good list of what primitives are available
<daveshah> although, of course, it doesn't tell you which will actually work
* ylamarre was actually joking.
<ylamarre> But turns out, code IS the doc in this case...
<emeb> daveshah: cool
<emeb> ylamarre: I figured you were actually right.
<emeb> the resource util pg for my blinky design: https://pastebin.com/9BRQpEbR
<tpb> Title: Info: Device utilisation: Info: ICESTORM_LC: 28/ 3520 0% Info - Pastebin.com (at pastebin.com)
<ylamarre> emeb: From what I remember icebox.py is quite nice to go through. Not too difficult to read last time I checked.
<emeb> so looks like all the stuff I care about is there.
<ylamarre> But that was like 3 years ago when there was only support for ice40LP/HX
<emeb> looking at it now - it's a big file but not hard to navigate.
<emeb> heh - u4k extra bits db "made up" - I guess that means they don't actually work.
<corecode> yea i didn't bother with trying them for a different footprint
<emeb> heh, yeah. the other footprints are not super easy to design with.
<emeb> I've got one of the "official" Lattice breakouts for the u4k and it's got the little WLCSP-36 part. Hard to imagine the kind of PCB rules you'd need to use that.
<corecode> yey so you can port for that footprint
<emeb> lol yes - if I knew WTF I was doing. :)
<corecode> yea that's how i started
<emeb> I know that clifford wrote up some #exactsteps for the the process of adding stuff a few years back. I wonder if those still apply.
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<corecode> so if you just want to map out connections, just instantiate the IP core and look at the explain output
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<emeb> corecode: for the n00b, which tool generates explain?
<emeb> derp - icebox_explain. :P
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<corecode> :D
<emeb> is it my imagination or are the cell coords given by explain off-by-one from those displayed in the icecube floorplanner?
<emeb> nah - they're fine.
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