clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> For https://gist.github.com/promach/1854bb054bb751fdfe02a3e655266e8e#file-async_fifo-sv-L171-L197 , is it alright to have the following warnings ?
<promach> SBY 16:10:28 [async_fifo_proof] base: Warning: Replacing memory \fifo_data with list of registers. See async_fifo.sv:129
<promach> SBY 16:10:28 [async_fifo_proof] base: Warning: Async reset value `$eq$async_fifo.sv:189$82_Y' is not constant!
<promach> SBY 16:10:28 [async_fifo_proof] base: Warning: Async reset value `$eq$async_fifo.sv:190$83_Y' is not constant!
<promach> SBY 16:10:28 [async_fifo_proof] base: Warning: Async reset value `$eq$async_fifo.sv:175$75_Y' is not constant!
<promach> SBY 16:10:28 [async_fifo_proof] base: Warning: Async reset value `$eq$async_fifo.sv:176$76_Y' is not constant!
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<ZipCPU> Try rewriting thhose assertion blocks to use $global
<ZipCPU> Try rewriting thhose assertion blocks to use $global_clock
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<promach> ZipCPU: What about "Warning: Replacing memory \fifo_data with list of registers." ?
<ZipCPU> How big is your FIFO?
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<ZipCPU> Oh, and ... what solver are you using?
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<promach> ZipCPU: I am using yices
<ZipCPU> For a FIFO of length 8, replacing the memory with FFs makes good sense
<promach> ok
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