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<phire>
What's the best way to generate a netlist with proper names on the flipflops?
<phire>
Modify the proc_dff (and subsequent passes) to generate and perserve names?
<phire>
write some kind of post-processing script or pass that generates a name based on the output wires?
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<daveshah>
phire: imo, a fix that generated names for cells based on output wire name would be very useful
<daveshah>
s/fix/pass/
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<puddingpimp>
it seems like it would be useful if there was a traceable link from every AST node to the pass and input AST node(s) that produced it
<puddingpimp>
but I guess that presumes that the prior AST state is stashed away somewhere
<puddingpimp>
I'm just an observer and not that familiar with yosys internals
<phire>
The previous state is deleted on each pass
<puddingpimp>
I do know that, I'm part of the way through te yosys manual atm
<phire>
the src attributes really should be propergated to every single generated node
<puddingpimp>
so there is the HDL AST and then the yosys AST (from what I understand) does the HDL AST from the lexer stick around in memory?
<phire>
Well, you can save out the IL at any point and load it into a new instance of yosys later
<puddingpimp>
how early/late is the AST flattened, eg. if I have 4 instances of a module A, which has two instances of module B, is module A and B optimised once each and then flattened,
<puddingpimp>
or is the whole AST flattened before any later processing
<phire>
I think the typical workflow is to run the hierarchy pass early on before optimising, which I understand flatterns the design.
<daveshah>
read_verilog does by default elaborate & simplify the AST with the default parameter set for a module (turned of with -nodefer); but keeps the AST around in case the module is encountered with a different set of parameters
<daveshah>
hierarchy will elaborate all modules as instantiated with their parameter set
<daveshah>
flattening is optional at this point, and pretty much unrelated to elaboration of the AST
<phire>
One problem with the manual, is that it doesn't really give you much idea which passes you should be running in which order
<daveshah>
There is a bit on this in the appnotes at the end
<daveshah>
tldr; always run hierarchy and proc before anything else
<phire>
Yeah
<phire>
Right now I'm trying to generate nice looking schematics of my design