clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZipCPU> AARGGGHGH ... I HATE AXI!
<ZipCPU> Whoever wrote the specification for it, didn't want to be kind to any individual working with formal methods
<ZipCPU> How hard can it be to just verify a single (full) AXI4 slave?
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