clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<tnt> Is there anyway to make yosys search the parent verilog file directory for includes and not just the explicit -I path and the cwd ?
<tnt> Oh wait ... it might be doing that already.
<emeb> the thing that always gets me is the path to search for $readmem files - every EDA tool handles it differently so I always have to guess where to put them.
<tnt> Yeah that's my next thing to work out ...
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<corecode> emeb: they search in the current directory, but often that is where the auto-generated project file is
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<emeb> corecode: right - and on icecube for example it's hard to figure out where in the dir tree that is, so I end up having to guess how many "../../.." to put in the file name.
<emeb> would be nice if they'd just assume the mem files are in the same dir as the .v files.
<emeb> or give an option like for includes and libs
<corecode> yea readmemb should be relative to the source location
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