clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<corecode> so maybe i'm wrong
<corecode> but 0.8mm ball pitch, that's 1.13mm diagonal
<corecode> say 0.3mm land diameter, so that's 831um between lands
<corecode> 0.2mm via drill + 120um anular ring = 391um left
<corecode> which leaves 150um after 120um space
<corecode> so plenty room
<corecode> i might be missing something
<cr1901_modern> >to init BRAM from a file <--- $readmemh?
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<emeb_mac> corecode: yeah - a few years back I did the math on putting vias & traces between pads on BGAs and it was still feasible for 0.8mm pitch
<emeb_mac> cr1901_modern: yes - that works for the complete build process starting from verilog. question was if it's possible to change BRAM contents *after* the bitstream has been built w/o redoing the whole synthesis/pnr/etc.
<emeb_mac> would save some time for eg CPU code in BRAM ROMS
<cr1901_modern> emeb_mac: Yes, use icebram for that
<cr1901_modern> It is statistically extremely likely to work
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<cr1901_modern> even though it relies on seeing a bitstream pattern that may or may not be valid outside of bram
<emeb_mac> cr1901_modern: yep - will give it a try
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