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<plaes>
any idea whether there are boards that support muxing two hdmi streams into single one that also support open tools?
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<tnt>
plaes: don't think so. Only working open tools are ice40 and ecp5 (I mean those with enough maturity to go from .v to bitstream for that kind of non-toy project). ice40 is way too small for that. And I have not seen any ecp5 board with 2 hmdi in and 1 hdmi out.
<plaes>
ok, quick googling gave me Numato Opsis (with Spartan-6) and NeTV2 (with Artix-7 but not yet readily available)
<tnt>
yup those would have been my recommendations if you didn't require open tools.
<tnt>
but the netv2 is available afaik.
<tnt>
crowdsupply shows it "in stock".
<plaes>
hmm.. cool
<tnt>
I'd go with the netv2.
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<plaes>
ooh.. Project X-Ray
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<Postmanmods>
Hi everyone! I have a question about yosys synthesis process vs the icecube process... Have been banging my head against this for a while now and can't seem to find a solid answer.
<Postmanmods>
I have a verilog program that synthesizes in yosys in about 20 seconds and works fine on my ice40hx1k but takes ~3 hours to synthesize and uses 10,000% of my allocated LUTs on icecube2! What am I missing?
<tnt>
Postmanmods: you're probably relying on it to infer a RAM
<tnt>
and inferring stuff ... is ... unreliable depending on what the tool support.
<Postmanmods>
Bear with me as I am dipping me feet into FPGA for the first time with this project I have undertaken.
<tnt>
post your verilog somewhere
<Postmanmods>
kk just a sec... It has a lot of nested if statements which I hear is a big no no in verilog.
<ZipCPU>
Could also be the result of a multiply within the code as well.
<Postmanmods>
Will do. Is it an issue with my code or the way I configured the synthesis?
<tnt>
ZipCPU: why ?
<ZipCPU>
In particular, your design breaks rule #3--and so yosys cannot manage to turn it into a RAM
<ZipCPU>
tnt: His design cannot map to the iCE40 hardware as written
<tnt>
ZipCPU: yosys works fine, icecuble doens't AFAIU
<ZipCPU>
Heheh ... yosys has some fun little clean up pieces of logic that not all of the big synthesizers support
<Postmanmods>
Yeah, that's what I am trying to reconcile. The code compiles and works perfectly from spi flash.
<Postmanmods>
Grrrr, thats what I figured!
<ZipCPU>
You could make the #46-60 block work if you calculated the memory address combinatorially
<tnt>
ZipCPU: I don't see why it couldn't map. A mux on the write address input to switch between 0 and waddr would work fine.
<ZipCPU>
Yes, exactly--yosys does that, but many vendor synthesis tools will not
<ZipCPU>
Many of the vendor synthesis tools are *really* strict when about what logic will infer block rams and which logic will not
<tnt>
Sorry I misunderstood, I thought you said there was no way to produce logic what would implement that behavior.
<Postmanmods>
So I have a second question, this one about NVCM.
<ZipCPU>
tnt: I did say that, didn't I? But if it works in yosys and not the vendor tool, then that can't be it.
* ZipCPU
google's NVCM, gets: "Noe Valley Chamber Music"
<Postmanmods>
LOL
<tnt>
Well " His design cannot map to the iCE40 hardware as written" ... I understand this as there is not theoritical way you could map that verilog to an ice40 design that implements it.
* ZipCPU
tries duck duck go, gets "New Vision Christian Ministries"
<Postmanmods>
2x LOL
<tnt>
Non Volatile Configuration Memory
<ZipCPU>
tnt: Yes. That's usually what's going wrong, but ... not in this case. (i.e. I was wrong. Oops)
<Postmanmods>
Non Volatile Configurable Memory, for one time flashing
<Postmanmods>
*configuration
* ZipCPU
needs to step away ...
<tnt>
what about it ?
<Postmanmods>
Is it possible to generate a nvcm bitmap from yosys for an ice40?
<Postmanmods>
Or is that a vendor app only thing?
<tnt>
is the nvcm bitmap different from the normal bitmap ?
<Postmanmods>
I think? One sec, lemme double check.
<Postmanmods>
Oh jeeze, they might be the same. Lemme post a .nvcm file for reference.
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<Postmanmods>
Real quick, thank you sincerely. Learning FPGA is one HELL of a steep learning curve.
<ZipCPU>
tnt: The reason for my earlier answer was that I've been burned several times over by the fact that the iCE40 hardware requires that the output of any memory read be registered. I was a bit hasty, before looking at the code, to conclude that was the problem since it's a common ice40 problem that you have when porting "working" designs to the iCE40
<ZipCPU>
Postmanmods: I'm not sure I know the answer to that one. I've never successfully loaded an iCE40 from flash, more from a lack of trying than anything else
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<tnt>
ZipCPU: heh no worries. I actually misread you answer, I read "I didn't say that did I" instead of "I did say that, didn't I" :p so I guess we both read too quickly.
<ZipCPU>
Sometimes I think it's a trait of a "good" engineer. :D
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<tnt>
The 'reset to 0' of the read register is also a common reason bram mapping fails.
<tnt>
In general I put all my inferred logic in a separate module with just that in it to try and make it as easy as possible for the tool to notice.
<tnt>
But icecube is really dumb ... I mean even a non-power of 2 memory depth prvents mapping.
<emeb>
I've noticed that too.
<Postmanmods>
Ok so its most likely a case of lattice's sorftware being picky.
<Postmanmods>
So that means a code clean up if I want a well optimized bitstream?
<emeb>
AFAIK the NVCM on iCE40 is programmed with the same bitstream format you'd load into the RAM directly, or into external SPI flash. But iceprog doesn't seem to support talking to the NVCM and I've heard that there's some sort of special unlock sequence needed to access it.
<emeb>
All that, plus the fact that it's OTP and I've avoided it.
<tnt>
Someone just needs to sniff and document it ...
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<Postmanmods>
I actually jimmy rigged an ice40 with an rs2232 to interface with the spi. Diamond programmer actually sees it and writes the CRAM!
<Postmanmods>
Better than paying $200 for Lattice's overpriced POS...
<tnt>
you mean ft2232 ?
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<Postmanmods>
Oh thank you,yes.
<Postmanmods>
Not serial lol
<Postmanmods>
I'll let you guys know what I find in my NVCM adventures. It would be really helpful for to use for some applications.
<emeb>
Cool.
<emeb>
It would be great for a default bootloader
<emeb>
and of course for low-cost / high volume stuff that's not expected to change. But who in this space ever does that? :)
<tnt>
emeb: unfortunately if NVCM is enable WARMBOOT doesn't work :/
<emeb>
tnt: ouch! missed that detail.
<tnt>
yeah :/
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<emeb>
So if the NVCM is enabled you can't use external SPI flash - only option is slave configuration.
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<emeb>
Interesting reading about Cold Boot mode - wondering how the device differentiates between an external SPI flash that has the "Cold/Warm Boot applet" and one that's just raw bitstream.
<emeb>
must be some reserved bits in the start of the bitstream...
<Postmanmods>
No no, I was reading about a dual boot feature... Can't back that up with a source rn but I think it may be possible.
<Postmanmods>
It is also an option in the Diamond programmer utility so there's that too.
<tnt>
SB_WARMBOOT and the multiboot header.
<Postmanmods>
Ah, right
<tnt>
you can specify 5 images in a header at the beginning of flash. First one is the one loaded by default. Then via the warmboot primitive the design inside the fpga can trigger a reload of any of the 4 other images.
<Postmanmods>
No documentation on that in my findings unfortunetly /:
<Postmanmods>
Dang... That would be so nice for prototyping.
<Postmanmods>
Have a polished design in the nvcm and rough code on the flash
<tpb>
Title: Imgur: The magic of the Internet (at imgur.com)
<Postmanmods>
Did I tag him correctly? Still used to discord.
<Postmanmods>
But you were correct, it was a blocking issue. Thank you so much for the advice, I spent an embarrassing amount of time on that...
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<ZipCPU>
Wha .. wha .. what happened! Did it work?
<ZipCPU>
Postmanmods: Did I miss something?
<Postmanmods>
Oh, the link you sent me
<ZipCPU>
Did that help?
<Postmanmods>
It turned out my issue was exactly what you said! I rewrote the blocking for the memory I/O and BOOM. Synthesized in icecube2 in 60 seconds flat with 30% LUT usage! :D
<Postmanmods>
Thank you so much, I could not understand why it was having such issue. You made my week man.
<ZipCPU>
Awesome!
<Postmanmods>
So you have a website with other resources like that?
<ZipCPU>
There's a lot of really useful information in those tutorial slides. You can find all of them from http://zipcpu.com/tutorial
<ZipCPU>
I've tested many of the designs on iCE40s too--although I have left some errors behind in most cases for you to find ;)
<Postmanmods>
I love the tuts, concise and to the point with examples.
<ZipCPU>
Thank you
<Postmanmods>
haha wonderful, debugging the tutorials code. Great way to learn!
<ZipCPU>
Well, isn't it?
<ZipCPU>
The last statistic I learned suggested you'd spend 30% writing your code, and 70% making sure it works
<ZipCPU>
If you are going to spend that much time getting it to work, shouldn't instruction be focused on that part of the design process?
<ZipCPU>
... or at least that was my thinking when putting the slides together
<Postmanmods>
Since I started learning about FPGA's I haven't really found any solid resources. Even the manufacturers info is meh at best.
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<ZipCPU>
Lol! Not only is their info meh, not all of their designs even work
<ZipCPU>
My most recent post at http://zipcpu.com discusses bugs in Xilinx's demo code
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<Postmanmods>
Its. The. WORST!
<ZipCPU>
Nah, it's not nearly that bad ... but you need to learn the ways of the formal methods
<Postmanmods>
So I have been only dealing in Lattice thus far. Which FPGA would you say is the best in general?
<Postmanmods>
Or your preferred?
<ZipCPU>
That's a hard question
<Postmanmods>
I know, different pros and cons, but what is your go to?
<ZipCPU>
I tend to prefer Digilent as a source for my boards. They tend to be well documented. That puts me often in the Xilinx camp. The problem is ... the open source tools don't work with Xilinx (much) yet
<ZipCPU>
So I've got a bunch of iCE40 and ECP5 boards on my desk that I'm working with as well
<ZipCPU>
They aren't nearly as well documented as the Xilinx ones are--or if they are I haven't found the key documents (yet)
<Postmanmods>
Oh hang, I need your opinion on a dev cyclone board (if its worth the $$ or not)
<ZipCPU>
I only have one cyclone board, the DE-10 Nano
<tpb>
Title: Terasic - All FPGA Main Boards - Cyclone V - DE10-Nano Kit (at www.terasic.com.tw)
<ZipCPU>
I do have a max-1000 board as well
<Postmanmods>
OH
<Postmanmods>
THAT SOLVES THAT LOL
<Postmanmods>
The link is to a DE10
<ZipCPU>
I wrote about my experiences with the DE10-nano on the blog
<Postmanmods>
No way
<Postmanmods>
Thats a weird coincidence...
<ZipCPU>
;)
<Postmanmods>
woah
<ZipCPU>
Not really ... I've done a *lot* of writing
<Postmanmods>
I highly appreciate the effort in this
<ZipCPU>
Thanks!
<ZipCPU>
The blog has lots of good stuff on it
<Postmanmods>
It's extremely well put together, I really dig the learning method. Resonates with me, ya now?
<ZipCPU>
That's my argument
<ZipCPU>
Here's my thesis: Verilog design needs to be taught hand-in-hand with how to work with a good simulator (Verilator) and formal tools. Without those, you'll end up like so many students at the end of a semester with a design that sort-of works
<Postmanmods>
Hmmm... Haven't gotten that far yet. Verilator simulates the ckt?
<ZipCPU>
Technically Verilator just converts Verilog to C++
<ZipCPU>
You can then use that for simulation. Supposedly (I haven't done the measurements) it's at least as good as if not better (i.e. faster) than the big vendor simulators