clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZirconiumX> So I found a Yosys bug, and bisected it to git commit e158ea20, but don't know how to minimise Verilog (I'm new to HDL)
<daveshah> Do you have any idea where the bug is happening?
<ZirconiumX> Let me just submit my bug report
<tpb> Title: Infinite loop while synthesizing for iCE40 · Issue #981 · YosysHQ/yosys · GitHub (at github.com)
<daveshah> Thanks
<ZirconiumX> An MCVE it is not, but I'm hoping it's a start
<daveshah> These kinds of bugs tend to be alright to solve without minimal code (stuff like sim/synthesis mismatches are where minimal examples are really needed)
<ZirconiumX> The git bisect commit looks odd to me; that's a logging commit
<daveshah> Yeah that's what I'm trying to work out
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<tpb> Title: bisect.txt · GitHub (at gist.github.com)
<ZirconiumX> Here's the bisect log
<ZirconiumX> daveshah: let me know if there's anything I can do
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<alcorn> ^^ in answer to my previous question, here is how you can setup Yosys to be used as a library: https://pastebin.com/aJ12EXUz
<tpb> Title: How to use Yosys as a library - Pastebin.com (at pastebin.com)
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