<adamgreig>
well before it worked and now it tries to use 65000 LCs instead of a few brams
<adamgreig>
so i guess i didn't notice the broken before but now it really is broken :P
<daveshah>
The iCE40 doesn't have a hardware transparent (write-through) BRAM mode
<adamgreig>
aha, that might be a good clue
<daveshah>
It is possible to fake this for a single clock domain, but afaik there is no guaranteed safe solution across clock domains to fake it
<daveshah>
Before Yosys tried, but this led to odd sim-synth mismatches
<adamgreig>
ack
<adamgreig>
I don't really care about write-through but I'm using nmigen and it might well be asking for that by default
<daveshah>
Hmm
<daveshah>
oMigen/LiteX definitely supports both
<daveshah>
I've seen both in its Verilog output
<daveshah>
not sure about nMigen, maybe it is an option?
<adamgreig>
it is an option on the read port
<adamgreig>
I'll see if that fixes things
<adamgreig>
yikes. it's certainly done something.
<adamgreig>
now I have hundreds fewer LCs and also no RAMs
<tnt>
adamgreig: what does the verilog look like
<tnt>
?
<adamgreig>
nmigen generates RTLIL rather than verilog though I do have a minimal test case
<adamgreig>
however I think I've solved it now
<adamgreig>
I have to set transparent=True on the read port to allow yosys to infer it for ice40
<adamgreig>
but then nmigen changes the read port enable from constant 1 to some undriven signal which resets to 0, so the read port was always disabled, which is why most of my design subsequently vanished
<adamgreig>
if I set transparent=False and assert rport.enable to 1 it all seems to work
<adamgreig>
so... user error I guess! albeit some slightly confusing api design
<adamgreig>
thanks daveshah!
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