clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<emeb> Hmmm... tried that on my up5k design and didn't see much effect. What's it supposed to help?
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<daveshah> mithro: no there isn't a nextpnr channel, but here is fine
<daveshah> In any case those two options are Yosys options and would affect QoR for any place and route flow
<daveshah> From my experience those options, particularly dffe_min_ce_use, don't always improve QoR and sometimes make it worse
<daveshah> Hence not making them defaults for the time being
<daveshah> In terms of nextpnr options, might be worth looking at the HeAP placer (-placer heap)
<daveshah> Doesn't always massively improve QoR, but is a lot faster on bigger designs
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<thasti> I've started work on adding support for wand/wor nettypes to Yosys (as i need it for code generated by a tool I can't easily change). Would the preferred solution deal with this during generation of RTLIL from the AST, or would it be cleaner to introduce an additional proc_-pass that creates $reduce_or/$reduce_and cells from these wires?
<daveshah> I'd probably favour putting it in RTLIL generation so it's not something that any other pass needs to be aware of in any way
<thasti> Makes sense. I'll try to see if I can wrap my head around the logic there.
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