clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<corecode> hi
<corecode> daveshah: do you know if i can drive the ice40 CDONE pin after config as I please?
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<tnt> corecode: depends on which ice40
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<corecode> tnt: which ones don't allow cdone traffic?
<daveshah> Most don't allow it
<daveshah> The one I know that does allow it is the UltraPlus in the WLCSP package
<daveshah> Might apply to other Ultra parts in smaller packages too
<corecode> so i don't mean driving CDONE from the fabric
<corecode> but combining CDONE and some other output pin to drive an MCU input - short on pins on the MCU side
<daveshah> I think CDONE is just an open drain output so that should be fine
<corecode> yea that's what i thought
<daveshah> I'm pretty sure that's actually what Lattice do inside the FPGAs that allow you to use CDONE as an IO
<tnt> corecode: you could also just ignore cdone if you don't care about it ...
<corecode> yea but that's not so good
<tnt> well I'm assuming you have some form of communication between fpga and mcu so you can signal proper boot using that.
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