clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> ZipCPU: not sure why yosys sby formal tool gave me that initial unknown thing. I will use iverilog and vivado simulator and solves most of the problems first
<ZipCPU> Yeah, me neither--since the formal tools have never given me 'x's before
<ZipCPU> Are you sure you had -formal specified in your sby file?
* ZipCPU is just making wild guesses at this point, having never seen this before
<tpb> Title: Spidergon Networks On Chip · GitHub (at gist.github.com)
<ZipCPU> Try using read_verilog -formal, and see if that makes any different from read_verilog -formal -sv
<promach> you mean without -sv ?
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<ZipCPU> Yes
<ZipCPU> It shouldn't make a difference since you don't have the sv license anyway
<ZipCPU> Although, you should know that the "read" command supercedes "read_verilog", but that discussion can wait for another day
<promach> I guess the issue lies somewhere else other than the sby file ;|
<promach> :|
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