clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<tpb> Title: Spidergon Networks On Chip · GitHub (at gist.github.com)
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<ZipCPU> promach_t: Because you never initialized the signal
<promach_> ZipCPU: huh ?
<promach_> no
<promach_> see the other flit_data_output signals
<promach_> only flit_data_output<3> has unknown signal
<ZipCPU> Wheres the initial statement giving it an initial value?
<ZipCPU> I looked and didn't see it
<promach_> ZipCPU: I have added initial flit_data_output[port_num] = 0; , but same "xxxxx" unknown signals
<ZipCPU> That's the problem. Keep working with it, and you should have it working
<promach_> ok, but I am not sure why the initial statement is not helping
<ZipCPU> I'd have to see more details to know
* promach_ will leave this piece of verilog code until monday morning
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