clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach3> Why `BB_dq` is not part of design ?
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<promach3> it is located here : https://github.com/YosysHQ/yosys/blob/master/techlibs/ecp5/cells_io.vh#L10 , but how do I actually instantiate this special module ?
<Lofty> promach3: that module just wraps a TRELLIS_IO; use that instead
<promach3> Lofty: what do you mean ? I am bit confused
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<Lofty> Use TRELLIS_IO not BB
<promach3> you mean TRELLIS_IO BB_dq (); ?
<promach3> Lofty: still same error
<Lofty> Did you include cells_sim.v in your SBY config?
<promach3> which exact cells_sim.v should I download from github ?
<promach3> Lofty:
<Lofty> It's the ECP5 one
<promach3> Yosys has only limited support for tri-state logic at the moment. (cells_sim.v:401)
<promach3> Lofty: smt2: ERROR: Unsupported or unknown directionality on port B of cell ddr3_memory_controller.BB_dqs_n (TRELLIS_IO).
<Lofty> Then evidently you can't have inout ports in SBY, so you'll need to figure out a way of removing the input buffers
<promach3> what ?
<promach3> why remove buffer ?
<promach3> I need tristate for DDR3 RAM application
<promach3> Lofty:
<Lofty> As I mentioned
<Lofty> You can't have inout ports
<Lofty> So you can't have tristate buffers
<promach3> thus yosys gave warnings about limited support for tri-state logic
<Lofty> Yosys does kinda accept tristate logic
<Lofty> But in this case, it's not really relevant
<promach3> but why it failed in my situation ?
<promach3> ok, I suppose yosys formal engine does not yet support tri-state logic
<promach3> Lofty:
<Lofty> Well, no
<promach3> did I conclude it correctly ?
<Lofty> In this case, the error is coming from the Yosys smt2 backend
<Lofty> Where I'm assuming an inout is unrepresentable
<promach3> smt2 is related to formal
<Lofty> Yes, I'm assuming it's a file format
<promach3> ok
<promach3> so, how do I work around this situation ?
<promach3> Lofty:
<Lofty> ... remove the buffers
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<Lofty> Like I said
<promach3> DDR3 require tri-state buffers
<promach3> cannot remove tri-state logic
<Lofty> Yes, but in a formal context you don't need them
<promach3> ok, I see
<promach3> let me think how to represent tri-state for formal
<Lofty> Well, you can't.
<promach3> Lofty: so, maybe I could assume(some values) for the input direction ?
<Lofty> if (direction) assert(output condition) else assert(input condition)
<Lofty> Or something
<promach3> cool
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<cr1901_modern> mwk: Re: the VPR mode in my machxo2 PR... it has become clear talking to symbiflow folks that I didn't actually understand the purpose of the code I was copying, so... oops on my end :P. In the next round of PR, I will remove the VPR mode
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