clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<Paul1> hello, i've got a question about using the additional inverted output pin in flip flops, the FAQ states "There is limited support for FFs with non-inverted and inverted outputs in Yosys"
<Paul1> i'm getting very weird results when i try to add these outputs to my library, minimal example here: https://paste.sh/YM68EEkE#SBhprH09QeQSULWku_zlfj0R
<tpb> Title: paste.sh · encrypted pastebin (at paste.sh)
<Paul1> and this is the graphviz output that I get: https://paste.sh/XBuQV90X#2IM8mKGbc51DYAuwKwx2p9w0
<tpb> Title: paste.sh · encrypted pastebin (at paste.sh)
<Paul1> note how there are only 2 flip flops for a 3 bit counter and Qn is shown as in input and there's a weird new signal that is used as an input but not driven by anything...?
<Paul1> i'm confused, what am I doing wrong?
<Paul1> everything works when i remove the IQN output from the ff in my library
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<Twix> You only have 2 flip flops because you use 2 bits in your counter. The third bit is not used. So it implements it using two flip flops(You are wrapping instant from 4 to 0. So you only have 4 states)
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<Paul1> no, this thing has 5 states, it wraps to 0 *after* the cycle where it's set to 4. the code basically sets zero = true for one cycle, then waits 4 cycles and repeat
<Paul1> it does the right thing if i just remove the IQN output pin in the library which isn't needed anyways
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<Paul1> found it: output was named "QN" in cells.lib and "Qn" in cells.v
<Paul1> feature request: make this fail early and hard
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<Lofty> Paul1: unfortunately I'm pretty sure failing there is a violation of the Verilog standard
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