FFY00_ has quit [Read error: Connection reset by peer]
lf has quit [Ping timeout: 250 seconds]
lf has joined #yosys
emeb has left #yosys [#yosys]
emeb_mac has joined #yosys
Degi_ has joined #yosys
Degi has quit [Ping timeout: 246 seconds]
Degi_ is now known as Degi
vidbina has joined #yosys
vidbina_ has quit [Ping timeout: 252 seconds]
citypw has joined #yosys
DaKnig has joined #yosys
emeb_mac has quit [Quit: Leaving.]
proteus-guy has joined #yosys
citypw has quit [Ping timeout: 240 seconds]
danvet has joined #yosys
vidbina has quit [Ping timeout: 265 seconds]
vidbina has joined #yosys
danvet has quit [Ping timeout: 240 seconds]
kraiskil has joined #yosys
citypw has joined #yosys
vidbina has quit [Ping timeout: 260 seconds]
DaKnig has quit [Ping timeout: 240 seconds]
kraiskil has quit [Ping timeout: 252 seconds]
kraiskil has joined #yosys
citypw has quit [Ping timeout: 240 seconds]
vidbina has joined #yosys
moony has quit [Ping timeout: 240 seconds]
moony has joined #yosys
vidbina has quit [Ping timeout: 240 seconds]
FFY00_ has joined #yosys
vidbina has joined #yosys
Paul1 has joined #yosys
<Paul1>
hello, i've got a question about using the additional inverted output pin in flip flops, the FAQ states "There is limited support for FFs with non-inverted and inverted outputs in Yosys"
<Paul1>
note how there are only 2 flip flops for a 3 bit counter and Qn is shown as in input and there's a weird new signal that is used as an input but not driven by anything...?
<Paul1>
i'm confused, what am I doing wrong?
<Paul1>
everything works when i remove the IQN output from the ff in my library
unkraut has quit [Quit: leaving]
unkraut has joined #yosys
s_frit has quit [Remote host closed the connection]
s_frit has joined #yosys
<Twix>
You only have 2 flip flops because you use 2 bits in your counter. The third bit is not used. So it implements it using two flip flops(You are wrapping instant from 4 to 0. So you only have 4 states)
Forty-Bot has joined #yosys
vidbina has quit [Ping timeout: 265 seconds]
emeb_mac has joined #yosys
vidbina has joined #yosys
dxld has quit [Ping timeout: 245 seconds]
dxld has joined #yosys
danvet has joined #yosys
adjtm_ has quit [Remote host closed the connection]
adjtm_ has joined #yosys
<Paul1>
no, this thing has 5 states, it wraps to 0 *after* the cycle where it's set to 4. the code basically sets zero = true for one cycle, then waits 4 cycles and repeat
<Paul1>
it does the right thing if i just remove the IQN output pin in the library which isn't needed anyways
adjtm_ has quit [Remote host closed the connection]
adjtm_ has joined #yosys
adjtm_ has quit [Remote host closed the connection]
adjtm_ has joined #yosys
adjtm has joined #yosys
adjtm_ has quit [Ping timeout: 240 seconds]
adjtm has quit [Remote host closed the connection]
adjtm has joined #yosys
adjtm has quit [Remote host closed the connection]
adjtm has joined #yosys
danvet has quit [Ping timeout: 246 seconds]
<Paul1>
found it: output was named "QN" in cells.lib and "Qn" in cells.v
<Paul1>
feature request: make this fail early and hard
adjtm_ has joined #yosys
adjtm has quit [Ping timeout: 246 seconds]
kraiskil has quit [Ping timeout: 265 seconds]
chipb has joined #yosys
<Lofty>
Paul1: unfortunately I'm pretty sure failing there is a violation of the Verilog standard
s_frit has quit [Remote host closed the connection]