clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<develonepi3> Hello All, Trying to update (icestorm c49586 nextpnr 4419c3 yosys d6d5c2) icestorm built ok when trying to build nextpr "cmake -DARCH=ice40 ." -- Using iCE40 chipdb: /home/devel/nextpnr/ice40/chipdb -- Configuring incomplete, errors occurred! Does anyone know what is the fix?
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<tnt> develonepi3: I'm going to bet you didn't recursive clone or checked out the submodules.
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<develonepi3> tnt: I did a clone of my repo and the added upstream and fetch then merge. Is this not the correct steps?
<tnt> there are submodules now. They need to be checked out. git submodule init && git submodule update
<develonepi3> tnt: in which repo icestorm or nextpnr or both?
<tnt> nextpnr
<develonepi3> tnt Thanks!
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<develonepi3> tnt: my nextpnr built ok.
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<develonepi3> tnt: Following yosys update, yosys -ql simple.log -p synth_ice40 -blif catzip.blif -json catzip.json -top toplevel ... ERROR: Assert `ifdef_already_satisfied' failed in frontends/verilog/preproc.cc:758. Any idea. I works okay with Yosys 0.9+1706 (git sha1 UNKNOWN, clang 7.0.1-8+rpi3+deb10u2 -fPIC -Os)
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<mwk> wtf
<mwk> develonepi3: congrats you found a bug
<mwk> now let's figure out what exactly is going on here
<develonepi3> mwk: this is line 758 log_assert(ifdef_already_satisfied);
<mwk> I figured
<mwk> ... why does this code even work
<mwk> hilarious
<mwk> I found an unrelated bug in this area of code, but still see no way to trigger that assert
<mwk> develonepi3: what code does this trigger on?
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<develonepi3> mwk: This is https://github.com/develone/catzip.git which was created from a version of icozip. catzip connect to a parallel RPi3. It has sdram instead of sram.
<develonepi3> I was trying to create a blif & json file.
<develonepi3> I use zipcpu & autofpga to create the toplevl.v & main.v
<develonepi3> mwk will the simple.log help. I can push to gist if you want.
<develonepi3> mwk: It was very early Parsing `main.v' using frontend `verilog' following toplevel.v
<develonepi3> mwk: The version of yosys is 03/24/21.
<develonepi3> mwk: Yosys shows 3 updates since my version. Would these be the fix.
<mwk> ... well that's a very simple reproducer
<mwk> develonepi3: thanks for the report, it'll be taken care of
<mwk> ... oh gods how is this code this dumb
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