<azonenberg> My sch symbols are my own unwritten standard
<azonenberg> My footprints are generally targeting IPC recommended land patterns
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<whitequark> IPC?
<rqou> so i finally actually disassembled my junk 3ds that i intend to hack, and i immediately committed the classic nintendo handheld hacking mistake
<rqou> while futzing with the battery i blew the fuse :P
<digshadow> whitequark: some sort of electronics manufacturing standards body, I hear them referenced for this and that at work
<whitequark> ah
<cr1901_modern> azonenberg, digshadow: Yes, I think that was it. The idea is, I want my FPGA board to have the least amount of problems, so I'm going to believe you when you say Kicad land patterns cause problems in practice
<cr1901_modern> So I guess I better look up the IPC standard or figure out if a free contrib library exists
* cr1901_modern grumbles to himself "should've used diptrace"
<digshadow> why did you go with kicad?
<digshadow> (not that I think kicad is an inherently bad choice)
<cr1901_modern> digshadow: Desire to complete this project using as many free/libre components as possible
<cr1901_modern> Icestorm for FPGA programming, libftdi to the FT232 to program the FPGA (slave SPI), Kicad for the PCB
<cr1901_modern> I gave Kicad a chance b/c azonenberg stood by it. I didn't realize how much work he had put in to make it do what he wants (doing all custom pads is almost a dealbreaker- that's a time-consuming process to do correctly)
<cyrozap> pointfree: I've gotten tired of working on my other projects, so I'll be working on KitProg/PSoC stuff this weekend. First task will be to fix the "reset -> segfault" issue since I don't think that will take too long. Next, I'm going to look into using the new DAP reg read/write commands (http://openocd.zylin.com/3778) with my J-Link to send a PSoC aquisition sequence.
<cyrozap> ...tired of working on my other projects *for now*...
<pointfree> cyrozap: great!
<pointfree> eric_j, our new contributor is causing me to revise the digital system layout map because of some info he found about the carry chains if you haven't seen it already: https://www.reddit.com/r/PSoC/comments/576in6/psoc_5lp_udb_placement_cheatsheet/
<pointfree> The .route files will now be useful.
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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vP6Ul
<openfpga-github> openfpga/master a3968d1 Andrew Zonenberg: gp4par: DRC messages are now indented. Added some skeleton code for PGA conflicts with IOB or ADC, but not yet functional as ADC isn't implemented.
<openfpga-github> [openfpga] azonenberg force-pushed gh-pages from 7f340dc to ca034d7: https://git.io/v6vmV
<openfpga-github> openfpga/gh-pages ca034d7 Travis CI User: Update documentation
<travis-ci> azonenberg/openfpga#93 (master - a3968d1 : Andrew Zonenberg): The build passed.
<eric_j> pointfree, great news!
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<eric_j> btw what PSoC programmer do you use?
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<azonenberg> Lol
<azonenberg> So apparently greenpak has crosstalk issues
<azonenberg> they recommend not putting high-speed signals on pins 7-8-9 when using the ADC
<pointfree> eric_j: I'm using openocd with the KitProg that is attached to that $10 CY8CKIT-059 (PSoC 5LP devkit). https://github.com/azonenberg/openfpga/wiki/UDB-%26-Routing-Examples
<eric_j> ah nice
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<carl0s> pointfree, do you know when OOCD 0.10 will be released?
<openfpga-github> [openfpga] azonenberg pushed 4 new commits to master: https://git.io/vP6TG
<openfpga-github> openfpga/master d8fcae9 Andrew Zonenberg: gp4par: DoPAR() now returns false on DRC failure
<openfpga-github> openfpga/master 7e9e594 Andrew Zonenberg: gp4par: Added DRC check for DAC1 + PGA conflict
<openfpga-github> openfpga/master 143f36a Andrew Zonenberg: gp4par: DRC now return false instead of terminating app when it fails
<pointfree> carl0s: I don't know, but openocd makes a release every few months: http://openocd.org/doc/doxygen/html/releases.html#releasewhen
<pointfree> For now I would just get the vcs copy as described on the wiki page if you want to try it.
<openfpga-github> [openfpga] azonenberg force-pushed gh-pages from ca034d7 to f8e8934: https://git.io/v6vmV
<openfpga-github> openfpga/gh-pages f8e8934 Travis CI User: Update documentation
<travis-ci> azonenberg/openfpga#94 (master - ab41900 : Andrew Zonenberg): The build was broken.
<carl0s> i did followed the instructions but i'm getting a weird error when i try to pull the most recent changes, idk if it's because the pull --rebases
<carl0s> can't remember the exact error, just installed 4.0, did you find usefull the cyvis and cysem files?
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<pointfree> carl0s: When did you try to get the git copy of openocd? I updated a patch set on that wiki page 22 days ago. "3432/14 --> 3432/18"
<carl0s> longer than that, like 3 months ago
<carl0s> from what i understand i only have to pull changes from the ref/changes?
<carl0s> sorry for the silly questions but i'm not very expert on git, only know how to pull, push, create PR lol
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<pointfree> The commands exactly as they appear should indeed work.
<pointfree> git clone http://openocd.zylin.com/openocd; cd openocd; git pull http://openocd.zylin.com/openocd refs/changes/21/3221/13; git pull --rebase http://openocd.zylin.com/openocd refs/changes/32/3432/18
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<pointfree> I enabled cysem/cyvis in PSoC Creator 4.0 but I didn't see the files after building or saving for some reason. Do you?
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vP6T9
<openfpga-github> openfpga/master b7c2a22 Andrew Zonenberg: greenpak4: Added DRC checks for PGA pseudo-diff + DAC0 simultaneously enabled. Added workaround for static analysis false positive.
<pointfree> ./bootstrap; ./configure --enable-kitprog; make
<openfpga-github> [openfpga] azonenberg force-pushed gh-pages from f8e8934 to 34d7708: https://git.io/v6vmV
<openfpga-github> openfpga/gh-pages 34d7708 Travis CI User: Update documentation
<travis-ci> azonenberg/openfpga#95 (master - b7c2a22 : Andrew Zonenberg): The build was fixed.
<carl0s> i do see them, those files are on the TopDesign directory
<carl0s> sorry, i read wrong, i did see them but not fully
<pointfree> I see it now. In the TopDesign directory.
<carl0s> can you generate cyvis and cysem files from projects did with Creator 3.3 and imported and recompiled with 4.0? i can not :/
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<rqou> random question azonenberg_work: what's the name of the interface chip that converts 4x 3.125 gbps lanes into 1x 10 gbps lane for sfp+?
<rqou> ethernet has too many layers
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<cyrozap> pointfree: I got reset working pretty reliably :)
<cyrozap> `reset halt`, `reset init`, and `reset` all work with the PSoC 5LP and KitProg FW 2.16
<cyrozap> Now I just need to test if it'll work ok on the PSoC 4
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<cyrozap> Hmm, it doesn't seem to want to work with the PSoC 4...
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<cyrozap> But I'm not actually sure it ever did in the first place, so that might not be a regression :P
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<pointfree> cyrozap: great news! I'm trying it out right now. Is your github copy up-to-date with those upstream patches from the wiki page? Perhaps your github copy could be a more reliable place to instruct people to clone from. Are you going go send your changes upstream?
<cyrozap> pointfree: just use the github repo to track individual changes with commit messages on my local git repo. I never rebase that on upstream master (I should probably merge those changes in at some point), so I don't suggest building from a direct clone of the branch. I push all the changes (patches split by commit) from that repo to OpenOCD's Gerrit instance (http://openocd.zylin.com/3221), so if you
<cyrozap> want upstream master + my changes, get them from there.
<cyrozap> *I just use
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<openfpga-github> [yosys] azonenberg pushed 32 new commits to master: https://git.io/vP6dN
<openfpga-github> yosys/master ed519f5 Clifford Wolf: Added "opt_rmdff -keepdc"
<openfpga-github> yosys/master 76352c9 Clifford Wolf: Added "prep -nokeepdc"
<openfpga-github> yosys/master ca54625 Clifford Wolf: Updated ABV to hg rev 2bc57cc30593
<openfpga-github> [openfpga] azonenberg pushed 6 new commits to master: https://git.io/vP6dp
<openfpga-github> openfpga/master 6febabb Andrew Zonenberg: greenpak4: added TODO comment for future routing changes
<openfpga-github> openfpga/master 13ebc54 Andrew Zonenberg: tests: Began work on DAC sawtooth test
<openfpga-github> openfpga/master 231eb5e Andrew Zonenberg: tests: removed obsolete comment
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* azonenberg is now working on the programmable delay lines for GP4
<azonenberg> should be pretty simple, not sure why i didnt do them yet
<whitequark> hrm
<whitequark> can the DAC take input from a counter yet?
<azonenberg> That's next on the TODO
<azonenberg> i have half the code written in my working copy
<azonenberg> ran into a snag b/c lost internet due ot the storm
<azonenberg> and couldn't pull latest yosys
<azonenberg> now that i'm back online i want to finish the pdelay since i have that mostly done too
<azonenberg> also, i have my DSO set up on the greenpak dev board
<azonenberg> i'm seeing some rather strange results
<azonenberg> in particular, emitting the same signal (2 MHz RC oscillator clock) from pins 19 and 20
<azonenberg> sorry, 18 and 19
<azonenberg> one pin has a nice clean waveform
<azonenberg> the other looks low-pass filtered in some way, like there's heavy capacitance on the line or something
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<whitequark> hm
<azonenberg> Gonna recalibrate my scope probes before i go chasing ghosts
<azonenberg> it was sitting around for ~6 months since i last used it, i was busy on s/w projects
<whitequark> are you sure there isn't a mechanical problem?
<azonenberg> So cal may have shifted
<whitequark> dirt in the socket
<azonenberg> Inconclusive so far, still investigating
<azonenberg> It just jumped out at me a few mins ago
<azonenberg> and i started poking
<whitequark> okay
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<azonenberg> Just recompensated my probes
<azonenberg> Let's see if that makes a difference
<azonenberg> I'm using the long clippy grounds, btw, but at 2 MHz i would not expect parasitcs to be a problem there
<whitequark> should not
<azonenberg> very interesting
<azonenberg> yeah, both probes still in 10x mode
<azonenberg> i tried different pins
<azonenberg> and i see the same artifact
<azonenberg> let me try probing the same pin with both probes...
<azonenberg> Confirmed its a measurement artifact
<azonenberg> same probe location
<azonenberg> weerird
<openfpga-github> [openfpga] azonenberg force-pushed gh-pages from 34d7708 to 12c7477: https://git.io/v6vmV
<openfpga-github> openfpga/gh-pages 12c7477 Travis CI User: Update documentation
<azonenberg> welp
<azonenberg> I unseated and reseated both probes on the scope
<azonenberg> it's less, but still there
<azonenberg> swapped them, it moved with the probe
<travis-ci> azonenberg/openfpga#96 (master - da55e91 : Andrew Zonenberg): The build was broken.
<azonenberg> cheap rigol probes will do that :p
<azonenberg> When i push on the strain relief boot for probe 1 right where it connects to the scope it works better, lol
<azonenberg> sounds like a failing probe
<azonenberg> high resistance internal connection, maybe a broken strand in the cable or something
<azonenberg> yeah the traces match up almost exactly now after nudging it a touch
<azonenberg> i really need to buy a nice scope
<azonenberg> only problem is, i'm trying to save for a house
<azonenberg> and spending a car worth of cash on a new DSO seems ill advised :p
<whitequark> meh, rigols are nice enough for me
<whitequark> for this kind of work
<azonenberg> yeah i might just buy a new probe
<azonenberg> it looks like ch1's probe is failing
<azonenberg> passive 100 MHz probes cant be too expensive
<azonenberg> not like a 10 GHz active differential probe :p
<whitequark> the rigol probes are like $20 per pair from amazon
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<azonenberg> got a link?
<azonenberg> i only see 300 and 500 mhz, or high voltage
<azonenberg> for more like $50 each
<azonenberg> my probes are RP2200
<whitequark> $20 was a high estimate, lol
<azonenberg> So, compatible but not OEM rigol
<azonenberg> i guess passive probes are pretty standard, just a BNC connector?
<whitequark> do you really think rigol manufactures probes itself?
<whitequark> they get it from the same place all other cheap DSO vendors do
<azonenberg> well i assume they contracted them out
<azonenberg> but had no idea where that was :p
<whitequark> there's no real difference between them i'm quite sure
<azonenberg> Either way for $13 hard to screw up
<whitequark> indeed
<whitequark> the passive probe also has X1/X10 switch
<whitequark> and a variable capacitor
<whitequark> but other than that it's just plastic
<azonenberg> Well yeah you need the compensation cap
<azonenberg> how does the attenuator work? just a voltage divider or something fancier?
<azonenberg> i've never looked into it
<whitequark> just a voltage divider afaik
<azonenberg> also, as much as i like silego's stuff
<azonenberg> i kinda feel like they took a "seat of the pants" design approach
<whitequark> azonenberg: https://www.elexp.com/Images/Importance_of_X10_Probes.pdf has schematics
<azonenberg> or at least, they expect the users to
<whitequark> it's pretty neat, the probe has the top part of the divider
<azonenberg> like, there's a lot of details that they dont include
<whitequark> and scope's input impedance has the bottom part
<whitequark> so you need to make sure the probe is matched with the scope
<whitequark> but AFAIK all cheap scopes have the same input characteristics anyway
<azonenberg> yeah thats the part i was unsure of
<azonenberg> i see 1M / 15 pF printed on my scope
<azonenberg> heck, most cheap scopes are probably rebrans of the same OEM :p
<whitequark> that definitely happens
<azonenberg> whitequark: anyway, back to what i was saying earlier
<azonenberg> silego seems to expect you to do "seat of the pants" design in their parts, i think
<azonenberg> like, they do not publish enough information for you to do proper static timing analysis
<azonenberg> also depending on which part of the datasheet you read, the typical delay per tap of the delay line (at 3.3V Vdd) is either 165 or 110 ns
<azonenberg> (I measure 176 for tap 1 on the particular die on my board right now)
<whitequark> interesting
<azonenberg> SLG46620V datasheet r085
<azonenberg> page 13 cites 165.49 ns typical for PDLY0
<azonenberg> at one tap
<azonenberg> ... oh
<azonenberg> wait a minute, derp
<azonenberg> So, for some reason gp4par is using a cross connection for routing the signal
<azonenberg> Which adds ~6 ns of delay
<azonenberg> which comes out to 171 ns
<azonenberg> i measure 172 after zooming in more on the scope
<azonenberg> So, that number seems accurate
<azonenberg> Table 98/99 list significantly smaller delay values