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<digshadow> azonenberg (and diamondman, rqou, cyrozap if interested): meet curryupnow at 6
<digshadow> in palo alto
<rqou> today?
<digshadow> yeah
<digshadow> mentioned it at the mtvre meetup
<rqou> hmm I'm still crashing Clifford's meeting with the research group at UCB :p
<digshadow> heh
<rqou> OK, I'll try to be there
<digshadow> I believe he's in town tomorrow too
<digshadow> fwiw
<digshadow> of course, clifford can crash the party too :)
<digshadow> we'll probably be playing with my new sem after dinner
<digshadow> trying to get it to work
<digshadow> but are flexible
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<rqou> is it the one on hamilton ave?
<rqou> digshadow-s:
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<digshadow-s> rqou: yeah
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<pointfree> Here's the papers on parallel logic synthesis that I mentioned further up and failed to provide links: http://odroid.0xffffffff.in/~deploy/parallel-synth/
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<digshadow-s> pointfree: see above
<digshadow-s> any interest in joining azonenberg for dinner
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<pointfree> digshadow-s: Yes, I would indeed be interested. 321 Hamilton Ave, Palo Alto, CA 94301?
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<digshadow-s> pointfree: yes
<digshadow-s> rqou: if you do end up coming and are running late
<digshadow-s> e-mail azonenberg or I to make sure we don't leave
<digshadow-s> he's arriving there about 5:30
<digshadow-s> i'll be heading over shortly
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<pie__> <digshadow> we'll probably be playing with my new sem after dinner
<pie__> say what now? xD
<pie__> when people just have SEMs lying around :P
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<cr1901_modern> Not everyone can be digshadow
<pie__> i finally bought a soldering iron the other day
<qu1j0t3> wellthat's a step
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<flaviusb> I am looking for a development board - something to get started with, given that I have minimal experience.
<whitequark> SLG44620V
<whitequark> and the "universal development board" from silego
<whitequark> there isn't really much choice
<whitequark> there's also SLG46621V, which is useful if you want level shifters
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<flaviusb> The universal development board being SLG4DVK1?
<flaviusb> Also, the GreenPak site seems to only have SLG46*, no SLG44* - is there some kind of secret site, or do I have to go to a 3rd party?
<whitequark> have you noticed the pagination at the bottom?
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<cyrozap> digshadow-s, pointfree: I'm in Texas, so I'm a couple of time zones away from the Bay Area :P
* cyrozap just finished reading the backlog after taking a break on projects for a few days
<cyrozap> pointfree: So the Forth code you just released takes the .route file and converts it into register settings? I don't know Forth so I'm having a pretty difficult time understanding it.
<flaviusb> I clicked through, did not find and SLG44*, just lots of different SLG46*
<flaviusb> I'm going to try out the SLG46621V. Many thanks for the advice!
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<digshadow> rqou (think it was you?) asking about delayering: https://twitter.com/johndmcmaster/status/798377303864537088
<whitequark> flaviusb: ah wait, SLG44?
<whitequark> greenpak4 is SLG46*, greenpak5 is SLG45*
<whitequark> their numbering scheme is weird
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<pointfree> cyrozap: The Forth code doesn't do any parsing of .route files and currently only has formulas for the Vertical Segment tiles.
<pointfree> I should clean it up a bit more. Once I've integrated my PLD synth code into that it should also be clearer.
<pointfree> The hv tile formulas aren't correct. I should look for mirroring again.
<pointfree> Once the .route file contents can be converted to registers and values, it shouldn't be difficult to place logic and plot routes. The routes will just need to be within the bounds and link up to each other.
<pointfree> Maybe if I can write formulas for the HS, HC, and PI tiles I can more easily connect the dots for the HV tiles.
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<flaviusb> whitequark: Thanks for the clarification - I was intensely confused by everything on the GreenPak website.
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