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<pie__> <jn> (off topic)
<pie__> <Cracki> excel wie nen fpga bespielen :D
<pie__> <Cracki> und jetzt riscv in excel
<pie__> <Cracki> wat indeed
<pie__> <jn> excel hat ja quasi schon (logik-)zellen
<pie__> <moho1> kann exel loops? (zelle a hängt von b ab, b von c und c von a)
<pie__> <Cracki> hat sicherlich auch irgendwelche funktionen, um LUTs trivial zu benutzen
<pie__> and so it goes lol
<pie__> oh shit wrong chan
<pie__> whoops
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<openfpga-github> [logtools] azonenberg pushed 2 new commits to master: https://git.io/vX75R
<openfpga-github> logtools/master c5a33fd Andrew Zonenberg: Merge branch 'moose'
<openfpga-github> logtools/master a916123 Andrew Zonenberg: Updated logtools for splash
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<openfpga-github> [logtools] azonenberg pushed 1 new commit to master: https://git.io/vX7d4
<openfpga-github> logtools/master 879545f Andrew Zonenberg: Fixed typo
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<openfpga-github> [logtools] azonenberg pushed 1 new commit to master: https://git.io/vX7FA
<openfpga-github> logtools/master ea1da3c Andrew Zonenberg: Fixed output#reloc typo
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<pointfree> "Cypress just bought Broadcom's wifi business and published their datasheets" https://www.reddit.com/r/linux/comments/5d7z0n/cypress_just_bought_broadcoms_wifi_business_and/
<whitequark> azonenberg_work: >moose
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<nats`> nop
<nats`> they bought the IOT businees of bcm
<nats`> business
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<pie_> pointfree, :O
<azonenberg_work> whitequark: ?
<azonenberg_work> oh
<pie_> "Not all of them. Just checked my BCM4360... yup, not there.
<pie_> " :/
<azonenberg_work> whitequark: So, i was just at an event called moosecon
<azonenberg_work> was trying to work on master but forgot i had some work on another computer
<azonenberg_work> so stashed it in a "moose" branch to merge from :p
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<pie_> azonenberg_work, o hai haha, ran across this by accident https://www.youtube.com/watch?v=Tq5-7szmxLA
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<pointfree> posting so I remember: The HV register bits each correspond to a line above and below a "vseg" line in a .route file. (vseg corresponds to a VS bit)
<pointfree> The direction of the HV switch (HV_L or HV_R) depends upon whether vseg has *_f or *_b affixed to the "vseg". vseg_*_f means HV_L and vseg_*_b means HV_R
<azonenberg> pie_: lol
<azonenberg> yeah there's a bunch of my talks around youtube now
<azonenberg> at least 2 or 3
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<pointfree> If the vseg line indicates we're going forward, (*_f or *_HV_L), then we evidently leave on the same block UDB=(_,_) that the vseg is on. If the vseg indicates we're moving backward (*_b or _HV_R) then we enter on the same block as the vseg.
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<rqou> offtopic: this is the most amazing (/s) UI i've ever seen: http://www.smogon.com/ingame/rng/dpphgss_capture_29.png
<carl0s> hi pointfree, i was looking the udb banks image, did you emember where it's available? Can't find it on the 5LP TRM.
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<felix_> rqou: speaking of ui fails: the hex editor i use failed at its job http://i.imgur.com/8fNjjmI.png (the 3rd line)
<rqou> wtf how?
<rqou> how did they manage to even do that/
<rqou> ?
<felix_> i don't know; maybe because 0xad is a non-printable ascii character? i'll send them a bug report maybe tomorrow
<rqou> anyways, the purpose of the tool that i linked the screenshot to is even more amazing
<rqou> it's a tool for predicting pokemon prng values
<pie_> i was about to guess that
<pie_> :P
<pointfree> carl0s: This https://rawgit.com/wiki/azonenberg/openfpga/images/udb-banks-and-routing.svg image is one that I produced by pasting together images from the patent and labeling it with current findings. You won't find it in Cypress documentation.
<pointfree> Is that the one you were talking about?
<pointfree> There's also eric_j's images from the reddit thread.
<pointfree> Maybe this one http://i.imgur.com/EPQpMYv.png from the PSoC Creator Manual?
<carl0s> Yes that's the image i'm talking about, just exported as png to print it, will take a look at eric_j images aswell
<carl0s> thanks, i saw it lastnight
<carl0s> placed a XOR gate with input pins at port12 and output pin at port15, expected to see the gate @UDB(0,0) but it ended @UDB(3,0)
<carl0s> now i'm compiling the project with a directive to place it @UDB(0,0) and see if the time report changes
<pointfree> carl0s: Is it possible to control placement? I didn't know that. It would be very useful!
<carl0s> there's a Directives tab on the cydwr menu
<carl0s> it would be great to do it graphically like the analog editor
<pointfree> Wow! Trying it out now. This will make things easier.
<pointfree> carl0s: The positioning of pin ports relative to DSI blocks is questionable because I think that's configurable with registers such as OUT_SEL0/OUT_SEL1
<eric_j> that's what i originally put together the diagram for... controlling placement
<pointfree> I have a theory that inputs (pin to dsi) are not so configurable so that what it's based on.
<pointfree> cyrozap: ^ I think you were asking about controlling placement some time ago.
<carl0s> hi eric_j , i'm now trying to place a counter7, did you tried controlling the placement of a logic gate? my first try was not successfull
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<rqou> offtopic: this is going to make me really productive today: https://goo.gl/photos/JdMzLYdtbbLPDE8f8 :P
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