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<peauters[m]>
hi all
<peauters[m]>
I have a quick q
<peauters[m]>
can anyone point me in the direction of some resources on setting up the different clocks and what they mean wrt timing outputs, e.g. SPI?
<peauters[m]>
I'm trying to get some sk6812 leds to work with the smart_led library and bumping into some timing issues
<adamgreig-m>
peauters: which stm32?
<adamgreig-m>
hah, nevermind
<peauters[m]>
f411
<adamgreig-m>
have you got the reference manual?
<adamgreig-m>
(RM0383)
<peauters[m]>
errrrr, I can grab it
<peauters[m]>
I'll go read =o)
<adamgreig-m>
SPI1 is on APB2, and SPI2 and SPI3 are on APB1 (you can tell by looking at the APB1ENR and APB2ENR registers)
<adamgreig-m>
the clock tree in Figure 12 shows the general setup
<adamgreig-m>
the SPI peripheral is clocked by either APB1 (SPI2/3) or APB2 (SPI1), and those are set by the PPRE1 and PPRE2 dividers (or set for you by the HAL, depending)
<adamgreig-m>
the dividers are from the "system clock" which is either the internal oscillator (HSI), your extenal clock (HSE), or the PLL driven by those
<adamgreig-m>
so.. lots of numbers to consider
<peauters[m]>
O_O
<adamgreig-m>
once you know what frequency APB1/APB2 is at, the SPI clock frequency is set by the BR field in the CR1 register, any of /2, /4, /8, /16, /32, /64, /128, or /256
<adamgreig-m>
the maximum sysclk is 100MHz, the maximum APB2 is 100MHz, and the maximum APB1 is 50MHz
<adamgreig-m>
so that's a common setup, in which case SPI1 is 100MHz/2 or /4 or /8...., and SPI2/SPI3 is 50MHz/2 or /4 etc
<peauters[m]>
and so when you set a frequency on the SPI in the hal, it can only approximate it according to how the clocks are setup?
<adamgreig-m>
you tell it a clock freq and a desired SPI freq, and it picks the best option
<peauters[m]>
but when I enabled pclk1 to 24.mhz it got wayy too long
<peauters[m]>
(I'm using SPI2
<peauters[m]>
* (I'm using SPI2)
<peauters[m]>
so I guess I should be setting pclk2?
<adamgreig-m>
SPI2 is on pclk1 and can't be changed
<adamgreig-m>
but pclk1 could run at 48MHz OK
<adamgreig-m>
so maybe you can write `.pclk1(48.mhz())` and keep sysclk at 48MHz too
<adamgreig-m>
then the SPI input frequency will be 48MHz, so it can run the SCLK output at 24MHz or 12MHz or 6MHz etc
<peauters[m]>
ok, I'll try that and take a look at the times on the logic analyser
<adamgreig-m>
(probably, if you don't put anything, it sets pclk1 to 48mhz by default?)
<peauters[m]>
thats probably why it was working better with it commented out
<peauters[m]>
so I need to change the frequency when creating the spi to try and get better times then, maybe
<peauters[m]>
I also could have fried one of the leds and thats why its not quite right
<adamgreig-m>
what are you asking for when you create it?
<peauters[m]>
3_000_000.hz()
<peauters[m]>
the data sheet for the sk6812s wants 0.32 and 0.64, us
<peauters[m]>
but the max for high is 1us
<adamgreig-m>
hmm, with either 24 or 48MHz it should be able to generate precisely 3MHz output, so it shouldn't make a difference if pclk1 is set to 24 or 48
<peauters[m]>
and I'm generating 1.06, which is why I think its drifting on the later leds in the line
<adamgreig-m>
if you run the SPI much faster, like 12MHz, you could probably generate more precise timings
<adamgreig-m>
I haven't looked at the smart led library you're using but assuming it outputs a sequence of bits to generate the right pulse lenths, with higher clock speed it gets more resolution per pulse, so maybe it will work better
<peauters[m]>
yer, I think the library would need updating maybe to take into account the shorter lengths, so it writes more bits
<peauters[m]>
I'll have a dig
<adamgreig-m>
do you tell the library a frequency or does it require a specific one?
<peauters[m]>
you give it an already configured spi to use
<peauters[m]>
let me dig a little more and test out some different values
<peauters[m]>
and see if its better
<adamgreig-m>
sure, good luck! looks like the library does just assume SPI is between 2.0-3.8MHz //! The spi peripheral should run at 2MHz to 3.8 MHz
<adamgreig-m>
uh, bad copy-paste, but anyway
<adamgreig-m>
so you'd think 3 would work but you don't have much fine control over it
<adamgreig-m>
perhaps you could do sysclk(50.mhz()).pclk1(50.mhz()) to get 50MHz SPI, then /16 would give 3.125MHz SPI clock, and maybe being a tiny bit faster will get you the timing you want
<adamgreig-m>
but yea, have a poke, see what the logic analyser says
<peauters[m]>
should I expect a bit of variation in the pulse widths (it could of course be my logic analyser - hantek 6022bl)
<adamgreig-m>
I wouldn't have thought so
<adamgreig-m>
How fast is the analyser sampling?
<adamgreig-m>
You would expect +-1 sample time
<peauters[m]>
16 MS/s
<peauters[m]>
I upped it to 24 MS/s and still see some weirdneess
<peauters[m]>
at the beginning of the 2nd led's data the first low is a bit long, but the led seems to not mind it
<peauters[m]>
at the beginning of the 3rd led's data the first low is infact high because it is too long
<peauters[m]>
and the same for the 4th
<peauters[m]>
all the other data seems fine
<peauters[m]>
and this seems to be the source of my issue with the 3rd LED being yellow and not red, as it infact has a fair big green component
<peauters[m]>
ohhhhhh 2 secs
<peauters[m]>
i tried enabling the pull up resistor, just in case
<peauters[m]>
it even happens if I set all the leds as 000000
<adamgreig-m>
Are you able to prove the SPI sclk signal? It would show you when the bits are being output, perhaps the stm32 is delaying a bit between bytes
<peauters[m]>
I've not got it as NoSck at the moment
<peauters[m]>
sticking it on a pin would be a pain as its on my keyboard pcb
<peauters[m]>
the other option for this (and I discussed it a little with thalesfragoso) is not to use spi, but use pwm
<peauters[m]>
but i think to get that tight enough, I'd need to use dma
<peauters[m]>
which isn't implemented yet for stm32f4xx
<peauters[m]>
I think I'm going to try and give it a go