ChanServ changed the topic of ##yamahasynths to: Channel dedicated to questions and discussion of Yamaha FM Synthesizer internals and corresponding REing. Discussion of synthesis methods similar to the Yamaha line of chips, Sound Blasters + clones, PCM chips like RF5C68, and CD theory of operation are also on-topic. Channel logs: https://freenode.irclog.whitequark.org/~h~yamahasynths
<cr1901_modern> ej5: How are you handling CDCs between ISA bus and rest of the chip?
<cr1901_modern> err logic*, not chip
<ej5> i have two synch flops to get from the ISA bus control signals (memr/memw, etc) into the main clock domain
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<cr1901_modern> Something like this? https://www.eetimes.com/wp-content/uploads/media-1071289-apafig8.gif (Pretend A[0] and A[1] are D0 and D1 or other data signals)
<ej5> yea
<cr1901_modern> Well there goes my theory. It was a long shot (and a shower thought), but I thought maybe _part_ (not all of it) of this corruption could be explained by "data bus FF metastability".
<cr1901_modern> (not all of it b/c some of the characters being drawn don't look like something you'd find in a font ROM)
<cr1901_modern> ej5: Oh right, "fun fact"... I seem to VERY vaguely recall that you can't treat the OSC pin as in-phase w/ the bus clock pin, which is why I started thinking about your design today :P.
<cr1901_modern> I.e. "how would TubeTimeUS do it?"
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<ej5> yeah osc is a free running 14.318mhz osc on many mobos
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