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<
leowt>
how is the a10 network interface connected to soc?
<
leowt>
i dont see mii in a10 datasheet
<
mnemoc>
a separated phy chip is used
<
leowt>
mnemoc: how is it connected to soc?
<
leowt>
through what, i mean
<
mnemoc>
using the PA pins
<
mripard_>
leowt: MII
<
mnemoc>
leowt: the A10 a bunch of programable pin banks, called PA, PB, PC, ....
<
leowt>
but, thats nasty, dont?
<
mripard_>
mnemoc: he's talking about the bus used to communicate with the PHY, and you the pins that are used to wire that bus :)
<
leowt>
mripard_: yes =P
<
mnemoc>
I thought it was already clear it used mii :<
<
leowt>
mnemoc: but i dont understand, shouldnt mii be in a pinout?
<
mnemoc>
that's why I answered about the pins :p
<
leowt>
im confused
<
mnemoc>
the pins of the bank A can be configured to work as mii when set to mux 2
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<
leowt>
mnemoc: im so new on this ehehe
<
mnemoc>
leowt: btw, #linux-sunxi is a better place to ask about these things
<
leowt>
is there any performance downside in having it this way?
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