14:41 <leviathanch> focus_it: hi. we don't have a differential clock output for the RAM at the A31

14:41 <leviathanch> what should we do?

14:42 <leviathanch> put an inverter gate at the output of the SoC clock output? doesn't seem elegant...

15:19 <focus_it> levianthanch: the S0CK and S0CKB seem to be the differential pair. Likewise S1CK S1CKB for the second slot. Cannot use inverter - if anything a single drive to differential line interface converter - but reasonably sure the two pairs given are differential (poor documentation - may be email Allwinner for clarification - just explain to them you are designing a board).

15:28 <penguin42> ssvb: Ah fun with knowing how to optimisie routines not based just on a particular core name, but core versions - it's so hard!

15:28 <ssvb> penguin42: :)

15:29 <penguin42> ssvb: I seem to remember that there are some configurable flags for prefetch on A8 as well and then it's just down to whether the firmware (or uboot??) set them

15:30 <ssvb> for cortex-a8 the important configuration bit is L1NEON

15:31 <ssvb> if it is set, NEON memory accesses go through L1 cache, which is blocking on cache misses

15:31 <ssvb> if it is not set, then NEON can bypass L1 cache and stream data from/to L2 cache or memory

15:52 <OmegaPhil> http://tech.slashdot.org/story/12/12/04/1748232/toward-an-fsf-endorsable-embedded-processor <- Just read this, sounds awesome - has any of the funding materialised?

16:03 <penguin42> hmm someone else claiming that an 8 core 800MHz thing can take on an i7 - sorry, I call bollocks

16:04 <penguin42> oh, it's that one again - old news

16:04 <OmegaPhil> yeah, was just posted in the FSF channel

16:04 <OmegaPhil> (an article on l.kcl's site that I then googled to get at that)

16:05 <OmegaPhil> Called for $10million funding :)

16:06 <buZz> sounds like another 'OMG MIPS IS AWESOME' project

16:17 <ssvb> OmegaPhil: isn't this a news from 2012?

16:20 <OmegaPhil> Yes