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<
jn__>
oh, you're adding an apple silicon device model to qemu?
<
sven>
well... so far i've just hacked up m1n1 :D
<
sven>
i was actually trying to add basic mmu support to m1n1 but my apple silicon mba is RMAed right now
<
sven>
so... qemu to the rescue
<
dhewg>
there's always another yak
<
dhewg>
but nice, i guess that speeds up that slow decompression step alot?
<
sven>
that's what i'm hoping, but we'll see
<
sven>
i also wanted to understand how the aarch64 mmu works
<
jn__>
does arm64 support caching without mmu?
<
sven>
i'm not 100% sure but i don't think so
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<
winocm>
it does not do that
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<
modwizcode>
Oh cool you're working on that too sven?
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<
never_released>
jn__: No.
<
never_released>
all memory is device memory with MMU off :P
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<
winocm>
sven: qemu does not properly model MMU attributes or caching for memory
<
sven>
winocm: i actually expect this to crash horribly on real hardware :D
<
marcan>
sven: dammit, you beat me to it :D
<
marcan>
I was thinking of writing that
<
marcan>
will test it out tomorrow
<
never_released>
> qemu does not properly model MMU attributes or caching for memory
<
never_released>
unaligned accesses allowed to device memory for example :D
<
never_released>
and plenty of other sins
<
marcan>
jn__: nor does aarch32 for that matter, not usabl
<
modwizcode>
It would be fun to have a model in qemu anyway even if it would be hilariously slow
<
marcan>
at least the chips I've used (ARM926)
<
marcan>
this is why mini also uses the MMU
<
never_released>
modwizcode: lol, use KVM on other hardware :P
<
marcan>
I was just going to reuse the structure of that code :>
<
modwizcode>
If I had other hardware I wouldn't use qemu c;
<
never_released>
that said things there are fun, especially if you want to virtualise Rosetta
<
modwizcode>
I guess I do have the pi
<
never_released>
where you'll need Arm hardware with TSO or stronger
<
j`ey>
i had to give my arm64 workstation back :(
<
modwizcode>
I wonder if anyone else has made that besides these chips (TSO that is)
<
never_released>
modwizcode: sequential consistency as the memory model on the NVIDIA arm64 chips
<
never_released>
and TSO for the Fujitsu A64fx
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<
modwizcode>
Interesting
<
never_released>
(note NVIDIA as in NVIDIA-designed CPU cores, aka not the Tegra X1, but 64-bit K1 and Xavier)
<
never_released>
or of course you have an easy escape
<
modwizcode>
The X1 isn't an in-house core?
<
never_released>
VM having only a single core
<
never_released>
modwizcode: yeah X1 is A57
<
modwizcode>
I forget, what does the Switch/Pixel C use, I have a semi-broken Pixel C laying around I wonder if I could repurpose it at some point.
<
never_released>
modwizcode: yeah, those just use X1, 4xCortex-A57 + 4x phantom Cortex-A53
<
never_released>
that disappeared bit by bit in the TRM
<
krbtgt>
qemu is the zsnes of general purpose computer emulators
<
never_released>
on an off-topic note: Boot firmware for all Jetson Nano developer kits updated to relocate boot firmware to integrated QSPI-NOR.
<
never_released>
Jetson Nanos can now boot regular Linux distros through u-boot
<
never_released>
on SPI NOR
<
never_released>
no need for Nvidia's l4t anymore
<
modwizcode>
good news!
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<
thecake21[m]>
>and TSO for the Fujitsu A64fx
<
thecake21[m]>
interesting. sparc had tso too didn't it? A64fx would be an interesting chip to have access to
<
thecake21[m]>
and TSO for the Fujitsu A64fx
<
thecake21[m]>
interesting. sparc had tso too didn't it? A64fx would be an interesting chip to have access to
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<
bylaws>
<never_released "that disappeared bit by bit in t"> Do you know if it's actually enabled on foster? It isn't on icosa at least
<
never_released>
thecake21[m]: yeah SPARC did
<
never_released>
inherited from there
<
never_released>
bylaws: probably not on any Tegra X1 device
<
never_released>
but who knows
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