<fridtjof[m]>
EnAFP obviously enables secret hardware acceleration for the Apple Filing Protocol
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<dhewg>
needs mmu and caches
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<modwizcode>
bit offtopic, but I've been working on the qemu support and I found yesterday a bug in the exynos uart driver. Fixing the bug stopped qemu from dropping incoming data when the fifo isn't enabled, but causes the RX loop to stall really really bad.
<modwizcode>
I can't find any particular reason for it to be so bad. It's not buffered well but it should not be creating nearly this much overhead.
<modwizcode>
anyone have any experience with this? It's just a busy wait loop on the "RX present" register but it seems like there's some artificial delay in there I can't find. The TX path has no issue whatsoever
<jn__>
did you look at the uart driver as it appears in the latest linux release, or asahi's patched version?
<modwizcode>
Those all enable the FIFO iirc (or properly use interrupts) which has completely different behavior
<modwizcode>
(patched version?)
<modwizcode>
oh patched linux
<modwizcode>
anyway yeah those all use the FIFO and/or interrupts which have different behavior
<modwizcode>
Like I just tested enabling the fifo in uart_init in m1n1 and unlike before things seem to work almost as expected because the fifo code also reports to the normal status registers somewhat
<modwizcode>
Although if I send it a write that's at all bigger than the buffer it recieves no data but that could be a quirk of how netcat works for the simpler testing
<modwizcode>
It seems like it might be a deeper qemu thing because I can see it spinning on the RX status register in qemu by enabling traces and it's getting cleared in both FIFO&non-FIFO paths meaning that everything has been "processed" the whole behavior is very strange and seems broken
<modwizcode>
It could be that due to some quirk of the way the emulated exynos uart is implemented it causes issues with qemu, I wouldn't doubt it.
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<marcan>
modwizcode: the FIFO is enabled on real hardware I believe
<marcan>
already by the time m1n1 runs
<marcan>
I can try disabling it
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<modwizcode>
marcan: Yeah that's what I kinda figured
<modwizcode>
I'd be very interested in the io speed with it out
<modwizcode>
*off
<modwizcode>
But I think I mostly tracked down the actual issue to a qemu thing, basically multicore code-gen seems to have some issue where io never gets polled again. So it ends up polling only in these like once per 0.5s chunks, which with a buffer of 1 (without fifo) is unbelievably slow.
<marcan>
ah heh
<modwizcode>
If you run single threaded codegen or weirdly enable the monitor on stdio and then type random crap in on multithreaded it works
<modwizcode>
so whatever the monitor does kicks it when you type.
<modwizcode>
I'm still trying to find that, but of course that's not really a m1n1/asahi problem it's some kind of qemu problem. My solution was to hack in a like 16KB buffer, as long as your buffer is big enough to fit a whole write transaction, and the vcpu is scheduled in time to read it before the next one is pushed, the problem disappears :p