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<enunes>
rellla: btw, I have a fix/workaround for the regression you mentioned in the random deqp test, but I think it's something we could fix in ppir scheduler or even in nir
<enunes>
I think it's kind of an existing bug that was just exposed
<enunes>
my patches also fix a few other deqp tests that were failing even before the new liveness analysis implementation
<rellla>
enunes: nice, i'll give it a try once you pushed them
<enunes>
I'll give it a quick shot in seeing how hard it would be to improve nir to not emit that code
<enunes>
yeah that one, doesn't mention if it is a regression
<UnivrslSuprBox>
Apologies for taking pictures of the screen, but here's another problem. I'm not sure if it's the same or if it should be a new trace and bug report?
<enunes>
anarsoul: it's a read write emitted by nir
<enunes>
dead write*
<anarsoul>
I don't really understand why scheduler reorders it though
<anarsoul>
let's say we have: r1.xyz = ssa1.xyz
<anarsoul>
and then only r1.x is used
<enunes>
x and z are used in this case
<enunes>
y is dead
<anarsoul>
enunes: we need DCE
<enunes>
nir should do it, not us
<anarsoul>
it doesn't do per-component analysis
<anarsoul>
anyway
<anarsoul>
even if it's dead ppir compiler should be able to handle it
<enunes>
yeah in this case it's a bug in scheduler
<anarsoul>
why not to fix it there?
<UnivrslSuprBox>
Well, on the dim side, reverting 9bf210ba causes stack smashing
<enunes>
I didn't create a MR for that branch because I am looking into nir and ppir scheduler solutions
<anarsoul>
enunes: oh, OK
<anarsoul>
sorry for the noise then :)
<anarsoul>
enunes: it's still sounds like a bug in nir->ppir translation though, likely we're missing a dependency somewhere
<enunes>
nit works fine until there is a vec4->per-component translation, and nir dce doesn't catch that really
<enunes>
I think a good solution would be to improve nir dce to catch it
<anarsoul>
yes, but in addition to bug fix in ppir
<enunes>
it might be difficult because it might not be trivial to prove it's actually dead since it's not ssa
<anarsoul>
enunes: that's why we need DCE pass in ppir :)
<enunes>
DCE in ppir might be sort-of trivial with the liveness algorithm merged
<enunes>
just need a set to store dead things, which is pretty easy to detect
<anarsoul>
enunes: sounds good
<enunes>
and run a pass of that before regalloc
<enunes>
but we can only get rid of an instruction if all ops are dead
<enunes>
or need to remove an of and reschedule... then it starts getting bad
<anarsoul>
yes
<enunes>
an op*
<anarsoul>
that's why we need to rewrite scheduler :)
<enunes>
my plan for next task was to attempt a simpler scheduler
<anarsoul>
basically we should start with one op per instruction
<anarsoul>
then do liveness analysis
<anarsoul>
then optimization passes
<anarsoul>
then merging instructions
<anarsoul>
or rather
<anarsoul>
merge and/or order ops
<anarsoul>
merging and reordering may require doing liveness analysis several times
<enunes>
I wish I had the time to try all of that :) and possibly include spilling in the loop
<enunes>
hopefully there is a way to do this redesign one thing at a time, which seems more feasible
<anarsoul>
yeah
<anarsoul>
good thing is that our data structures don't need major redesign
<UnivrslSuprBox>
I have good news for you and bad news for myself. Reverting both commits at the tip of the liveness branch shows that indeed caused the weird colors
<anarsoul>
I'm not sure why it broke gpir compiler, likely there's some bug in it
<UnivrslSuprBox>
Sure, that's building now. In the mean time, I'm back with the liveness patches and I'll get you a trace of something that should have rounded corners
<UnivrslSuprBox>
Reminder, this is in the branch with the ppir changes *reverted*
<UnivrslSuprBox>
Not the new fixes sent here today
<anarsoul>
mariogrip: try with valgrind?
<anarsoul>
this backtrace isn't very helpful
<anarsoul>
rellla: so I checked hsl_to_rgb.vert with 6f394343b1f704f8b98a24add7f4106e72e2db7b and without it
<anarsoul>
without it we get more optimal nir code
<anarsoul>
with it there's some duplications
<anarsoul>
oh sorry
<anarsoul>
ah, it's actually correct
<anarsoul>
so this optimization results in suboptimal nir code
<anarsoul>
but yet it's correct
<anarsoul>
so it's a bug in gpir compiler
<anarsoul>
:(
<mariogrip>
So I hit a valgrind bug, seems like i never valgrind, as this version does not support ldpsw opcodes. but I need to contune that tomarrow, i need to get some sleep