ChanServ changed the topic of #lima to: Development channel for open source lima driver for ARM Mali4** GPUs - Kernel has landed in mainline, userspace driver is part of mesa - Logs at https://people.freedesktop.org/~cbrill/dri-log/index.php?channel=lima and https://freenode.irclog.whitequark.org/lima - Contact ARM for binary driver support!
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<anarsoul> yuq825: hi
<anarsoul> do you have a board with H3?
<yuq825> yeah
<anarsoul> can you try running dEQP-GLES2.functional.default_vertex_attrib.* on it?
<anarsoul> well, intermittently fails
<anarsoul> but I can't reproduce it on A64 :\
<anarsoul> rellla tried to reproduce it on A20 but it's also fine
<anarsoul> it's not urgent but it would be nice to figure out what's going on
<yuq825> OK, not now as I don't have it on hand
<anarsoul> it's unlikely to be attribute address alignment issue
<anarsoul> I tried this to verify different alignments: https://gist.github.com/anarsoul/1f85b9f705563211818a3b4f33f4b1aa
<anarsoul> and utgard seems to be dealing fine even with unaligned buffers
<anarsoul> *attribute buffers
<yuq825> interesting, I did not experiment much on the alignment before, just use 0x40 alignment as some address register don't have lower bits, but indeed not all of them
<anarsoul> attribute descriptors and varyings descriptors have to be aligned to 0x40
<anarsoul> so are varyings since literally anything that PP or PLBU consume need to be 0x40 aligned
<anarsoul> likely GP can write unaligned varyings but PP won't be able to read them
<anarsoul> since PP doesn't have varyings descriptor
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<rellla> anarsoul: it was an A10
<anarsoul> yet it's mali400
<anarsoul> and 32-bit
<rellla> i can see if my H3 is easy to setup and try it there, too.
<anarsoul> rellla: it's intermittent failure and it's hard to catch
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<rellla> just for the record :)
<rellla> for example:
<rellla> 0x90000105 - 0x90000108 also seems to be viewport, where bit 31 seems to indicate, that an address is passed, not the value.
<rellla> at the address we can find the value again.
<rellla> 0x90000103 and 0x90000104 also get an address passed and there we find another addresses, which are
<rellla> .frame.tile_heap_start for 0x90000103 and .frame.tile_heap_end for 0x90000104
<rellla> don't know if it's related but we should know of that :)
<rellla> yuq825, enunes ^^
<yuq825> i think I've seen this before when implementing glFlush
<yuq825> then I revert it due to the implementation is too complicated and can overflow PLB and heap
<yuq825> this is for the case: draw -> flush -> display -> draw -> flush -> display without clear
<rellla> ah ok. what is the advantage of that implementation then?
<yuq825> blob will save the previous PLB and GP PLB buffer when flush, then reuse with new draw command
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<rellla> which increases performance but is not necessary to get things run?
<yuq825> this can prevent reload the FB if the draw commands are simple
<yuq825> and can keep the depth order
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<yuq825> but can overflow the PLB and GP PLB if application does not clear and always do flush
<rellla> who decides when mali should go this way?
<yuq825> the OGL/EGL API
<yuq825> if user call glFlush, lima_pipe_flush has flags=0
<yuq825> if user call eglSwapBuffer, lima_pipe_flush has flag=PIPE_FLUSH_END_OF_FRAME
<yuq825> another thing is if user has call glClear in this draw
<rellla> so glFlush saves the state, eglSwapBuffer doesn't?
<yuq825> yeah
<rellla> is it worth to pick that up again then?
<yuq825> with glFlush, you can see 0xa0000107 do the save and 0x90000107 do the restore
<rellla> yes, found that
<yuq825> yeah, if we can figure out the overflow handling
<rellla> i didn't get still, what can overflow :/
<yuq825> and for correctness: one draw with glFlush, then another draw, with the FB reload way, the depth info is gone, with the save/restore way, I think it's kept
<yuq825> this plb_gp_stream
<yuq825> sorry, not this one
<yuq825> should be the PLB buffer
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<yuq825> if I remember correctly, PLBU will save the previous draw's commands in the PLB, then add new draw's commands, one PLB block is 512B, so there's limit on the commands can be appended
<yuq825> more accurately, not draw commands, just draw commands' PLB output
<yuq825> in the overflow case, maybe heap buffer is used, but heap buffer is also limited size
<rellla> the size of PLB block is hard limited?
<yuq825> it can go up, maybe 4096 max
<rellla> so we can try to dynamically allocate it?
<yuq825> then you need a way to know when to realloc it and how
<yuq825> also if 4096 is enough
<yuq825> maybe an interrupt like the LIMA_GP_IRQ_PLBU_OUT_OF_MEM
<yuq825> LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS maybe
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<anarsoul> rellla: enunes: if you folks are looking for another task there's https://gitlab.freedesktop.org/mesa/mesa/issues/1849 :)