ChanServ changed the topic of #lima to: Development channel for open source lima driver for ARM Mali4** GPUs - Kernel has landed in mainline, userspace driver is part of mesa - Logs at https://people.freedesktop.org/~cbrill/dri-log/index.php?channel=lima and https://freenode.irclog.whitequark.org/lima - Contact ARM for binary driver support!
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<rellla> anarsoul: btw, is there a way to workaround the 512 instructions limit of gp at all?
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<anarsoul> rellla: no, it's hard limit
<rellla> anarsoul: ok. dEQP-GLES2.functional.shaders.indexing.tmp_array.vec4_dynamic_loop_write_static_read_vertex hits that limit, but the root cause isn't the 512 instr limit
<rellla> ... as an example.
<anarsoul> yes, in this case it's compiler bug
<rellla> we have an issue, if the vertex shader gets an int uniform ...
<anarsoul> we talked with Connor about it few months ago
<anarsoul> rellla: it's not about int uniform
<rellla> what else?
<anarsoul> you can change it to float and it'll be the same :) moreover all ints are lowered to floats
<rellla> then it's about the uniform itself?
<rellla> i just can see, that https://pastebin.com/raw/mftqm1rf fails, whereas https://pastebin.com/raw/uR1GUTPt works
<anarsoul> no, it's about limited number of loads/stores per instruction
<anarsoul> i.e. more registers you use less likely scheduler will be able to schedule the program
<anarsoul> I'd say it's regalloc/scheduler issue
<anarsoul> IIRC we can store up to two vec4 regs and load 1 vec4
<anarsoul> the problem is that GP is scalar and so are our regs
<anarsoul> so in best case you can load 4 scalar regs, in worst - 1 (if all the regs are from different vec4)
<anarsoul> rellla: but so far I haven't seen any real-world app that hits this bug
<rellla> ok, thanks for the explanation
<anarsoul> feel free to poke it, maybe you'll find an easy solution, but I doubt there's one :)
<rellla> if so, i think i have to understand gp regalloc and scheduler first :)
<rellla> GP is one part of lima, i never looked into before :p
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