<Tony_>
naobsd, there are some tools from your country on my desktop. ;)
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<Tony_>
Pls congrats me. I fixed the backlight problem.
<Tony_>
ah ah ....
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<naobsd>
return to home...
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<AstralixNB>
field^MOP: I have never heared of IDB before seeing this RK tool. According the results of reverse engineering, IDB should be something like "inode data base". However IDB is the database that represents the flash translation layer (FTL) and tracks the information which logical sector of the "disk" is assigned to which physical sector. This includes the defects management too.
<AstralixNB>
The IDB is stored at the end of the physical NAND and it's size almoste doubled at Loader v2.xx compared to Loader v1.xx
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<karlp>
facny scope Tony_ :)
<Tony_>
karlp, sorry my poor English, I can't understand your sentence. ;)
<Tony_>
are you talking about my workstation ?
<karlp>
yes, I was admiring your lecroy :)
<AstralixNB>
It is often the reason people get messages "NAND write error" or "Flash compare error" or similar messages from flash tools. This happens when the images end reaches into this IDB erea.
<Tony_>
karlp, ah . It help me a lot.
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<naobsd>
mmm
<naobsd>
on rk3066, GPIO3 A7 func1 is SDMMC0_PWREN
<naobsd>
should it be configured to func1? then who control this pin?
<naobsd>
or configure it as gpio and control it from kernel?
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<naobsd>
let's use it as gpio....
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<mmind00>
naobsd: correct (mainline-)handling for this gpio power switch is gpio -> fixed-regulator -> vmmc-supply for mmc host ... see vcc_sd0 in rk3066a-marsboard.dts for example
<naobsd>
mmind00: thanks, I know that way, I just wandered what func_1 does...
<naobsd>
wondered
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<naobsd>
mmind00: dd79c0bea70516f52edc01c32e3f1ac7f20751a5 clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some plls causes
<naobsd>
rockchip_pll_wait_lock: timeout waiting for pll to lock
<naobsd>
rockchip_rk3066_pll_set_rate: pll did not lock, trying to restore old rate 768000000
<naobsd>
on my PX2 board
<naobsd>
PX2 may use different parameter
<naobsd>
I have to check 3.0 kernel...
<mmind00>
naobsd: sometimes they use lightly different pll types ... see rk3188 vs rk3188a ... also I wouldn't trust the rk3066 clock tree to match your px2 soc
<naobsd>
px2 source tree is basicalle s/rk3066/rkpx2/g
<naobsd>
but 2 unique difference, and 1 of 2 is pll table
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<naobsd>
no, it uses same table as rk3066 :(
<naobsd>
oh, now I can see USB-SATA...
<naobsd>
chipspark's rayeager px2 board needs to toggle some gpios...
<naobsd>
usb hub
<naobsd>
usb sata
<naobsd>
ethernet phy
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<naobsd>
mmind00: there is a reset gpio, basically just set high at boot time is enough, then only pinctrl pcfg_output_high is enough? or should I prepare fixed-regulator for reset pin?
<naobsd>
it may need high -> low -> high at some point
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<mmind00>
naobsd: regulators are for gpio controlling power-switches (aka power-supply stuff)... reset gpios are a different (separate) issue
<naobsd>
for ethernet phy, it should be done in driver
<naobsd>
but I have no idea for on-board usb hub and on-board usb-sata bridge
<naobsd>
currently
<naobsd>
default state -> high is enough
<mmind00>
naobsd: ideally of course the driver should handle the reset handling ... there exist the reset framework but it currently does not have a driver for simple reset gpios (though the framework description explicitly mentiones reset-gpios)
<naobsd>
why I thought fixed-regulator is because
<naobsd>
"init start -> request power -> power-off to power-on" and "init start -> request power -> reset-asert to reset-deassert" is similar
<naobsd>
of course reset pin doesn't supply power...
<naobsd>
well
<naobsd>
for now, I need workaround
<naobsd>
and complete solution is not available for now
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<Astralix1>
field^MOP, I don't want to sound selfish, but the source of this knowledge is my experience with SLC drivers that I had in my former work.
<Astralix1>
The details matched the ones from sarg as we did some reverse engineering in parallel without knowing each other. But later we had some email contact.
<Astralix1>
And later naobsd came up with the same results.
<Astralix1>
And last not least these details where proved true by RK engineers.
<Astralix1>
mmind00?
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<mmind00>
Astralix1: present :-)
<Astralix1>
Cool!
<Astralix1>
Is there any access to a recent Android kernel for the 3288?