03:44 <ayaka> micken, sorry I went to sleep

03:49 <ayaka> micken, the Configuration Identification Register 0 is more likely to be a efuse register, telling the supporting standard of this hdmi phy

08:46 <micken> ayaka: I found out that i.MX6 uses the same controller so I can use the information from its docs

08:48 <micken> ayaka: I really hoped that the trm was right about default configuration. But it seems like it isn't and I have to walk thru the whole process (pixelclock, framecomposer etc etc )

08:53 <ayaka> micken, I see

15:39 <micken> ayaka: actually , we have a driver for i.MX6 HDMI , looks like it can be reused with very little effort

15:41 <micken> less for me to type in \o/

16:57 <ayaka> micken, nice

17:46 <ayaka> mmind00, may I ask you something about the clock source in kernel?

17:47 <ayaka> I want to raise the clock of the VPU IP, although the current source is pll_cpll and its frequency is 400MHZ, should be enough

17:48 <ayaka> also the rockchip kernel 4.4 now change to the other source. I wonder how does it work

19:42 <mmind00> ayaka: in the devicetree you have assigned-clocks, assigned-clock-rate, assigned-clock-parents that can be used to change the clock-hierarchy

19:43 <mmind00> "assigned-clock-rates" of course

21:43 <micken> RISC OS 992MB

21:43 <micken> Cortex-A17 Processor

21:43 <micken> \o/