hno changed the topic of #linux-sunxi to: /Allwinner/sunxi development discussion - Don't ask to ask. Just ask and wait! - See | | Logs at
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<hno> Turl, what do you mean by tagging?
<hno> Down to 3339 / 3816..
<Turl> hno: gmail filters (or similar functionality on any mail client)
<hno> yea, it's filotered & sorted easily. But doesn't really help.
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<Turl> hi hipboi :)
<hipboi> Turl, morning
<Turl> hm, I suck at reviewing :) it took me 1h30 to write 4 emails
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<ganbold> hipboi: thanks a lot for cubie2, just received it yesterday
<hipboi> ganbold, yesterday?
<hipboi> ganbold, long time...
<ganbold> actually I didn't check my post long time :)
<ganbold> it must have arrived in June probably
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<WarheadsSE> hipboi: cubie2 support will be official in Arch shortly.
<WarheadsSE> (like, an hour at most)
<Turl> hipboi: mine is still in customs :) fun wait haha
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<hipboi> WarheadsSE, great news, thank you and your team
<deasy> on the a10 page there is an * aside of CEC support but nothing in the page about it
<Turl> deasy: I believe it technically can do CEC, but there is no driver and there's no well established api to implement one either
<Turl> I think rz2k did some work on it
<Turl> check the mailing list in any case
<deasy> ho no it was just for say than there is a * in the wind alone
<rz2k> cec was done by techn_
<Turl> deasy: maybe to symbolize that catch, even if it's not explicitely written
<rz2k> he took it from a10s sdk updates
<Turl> rz2k: thx for the info :)
<rz2k> you are welcome. also he had a branch on his github
<rz2k> with his experimental stuff
<deasy> bip bip hackers around spotted
<Turl> deasy: your hacker scanner should've been on fire since you arrived here :p
<Turl> night
<deasy> :)
<ganbold> Turl: btw, found user manual of A20 at
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<hipboi> yes, Turl, do you have permission to put it at
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<hno> hipboi, done.
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<hno> but a little confused about document date. Either has the date wrong or someone forget updating the document header..
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<hno> heh.. it's he doc header that is wrong.
<hipboi> no strange
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<oliv3r> too many mailing lists your subscribed too?
<oliv3r> hno: Turl what helps me is, i have a seperate mailbox for mailing lists
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<oliv3r> things that are directly important for me, I hope to be CCed on my non-list mailbox
<oliv3r> and it has the added benefit that I can actually use my email reasonably well on my phone :)
<oliv3r> as it stands, i have 2/3000 in my inbox :p
<oliv3r> and on my lists one it's 4/252
<oliv3r> but i move mails to subdirs once i'm done wtih them
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* rellla saw that mnemoc pushed recent patches to stage/sunxi-3.4 :) time to pull it
<oliv3r> rellla: test test test it
<oliv3r> our stage is a bit shaky atm
<oliv3r> and time to read a20 manual
<rellla> not at $work$
<oliv3r> <- work
<oliv3r> ohh yes! a20 user manual
<oliv3r> hipboi: thank you!!
<oliv3r> lets hope that the a20 manual fills in missing bits and pieces
<oliv3r> looks like a new manual tbh
<oliv3r> might not be copy/pasted?! almost unbelievable
<oliv3r> Videoengine is called 'phoenix 3.0' :D
<oliv3r> a20 has smart card reader support, i don't think a10 had that
<oliv3r> if its integrateable with oscam, one can build a pretty badass settopbox with this chip :)
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<mripard_> arokux1: yes?
<oliv3r> 1 canbus got dropped
<oliv3r> mripard_: hey, did you read ^; we have a20 user manual now
<oliv3r> on
<mripard_> yep, just saw that
<mripard_> it's cool :)
<oliv3r> PWM looks like it's different, it seems to be like the sun6i pwm
<oliv3r> i think sun7i is a little hybridic between a10 and a31
<oliv3r> ssvb: usermanual says 256 KiB L2 cache
<oliv3r> shared between both cores
<oliv3r> Oh, we know that there is a HDMI register; was omitted in previous docs
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<oliv3r> emac and gmac are seperate register blocks
<oliv3r> strangly, a20 still has the GPS block; but afaik this has been removed from the pinmuxes
<oliv3r> guess not
<hno> oliv3r, the lists isn't that big problem, but yes it adds up to volume.
<oliv3r> SCR is from A10; same register block as SmartCardReader
<oliv3r> :)
<oliv3r> time to wiki :)
<hno> oliv3r, the A20 manual fills in several missing pieces.
<oliv3r> yeah it does
<oliv3r> you've been reading it too?
<oliv3r> i'll add things to the memory map so we can get a better picture
<oliv3r> since we officially have the manuals now; the subpages aren't as important anymore
<oliv3r> I guess only if it contains additional information or fixes bugs
<oliv3r> kinda a lot of work wasted :(
<arokux> hi mripard_, where these clock should go to? should they been added to the drivers/clk/sunxi/clk-sunxi.c?
<oliv3r> arokux: poke turl, he's the clk maintainer :p but yes
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<arokux> oliv3r, ok! thanks
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<hno> oliv3r, yes very confusing about EMAC/GMAC.
<arokux> Turl, can you take a look at it? ---^
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<arokux> (at clocks, a bit higher in the messages)
<mripard_> arokux1: the clock "driver" should be in driver/clk/..., the clock definition, with its parent, rates et al. in the DT
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<oliv3r> hno: the intro even lists both seperatly, i haven't looked at the PIO map
<oliv3r> but maybe mii and rmii (gmac) are on the same pins, but different controllers
<oliv3r> it's silly really, as rmii can do 100mbit just fine
<arokux> mripard_, so usbc_phy_gate, ohci_phy_gate and usbc_phy_reset are different from ahb clocks?
<oliv3r> but if they are seperate pins, dual ethernet :)
<arokux> mripard_, oh, sorry, the others are also there. so you just haven't added usbc_phy_gate, ohci_phy_gate and usbc_phy_reset, right?
<mripard_> arokux: it looks that way yes
<mripard_> yep
<panda84kde> hi channel guys :)
<hno> oliv3r, afaik there is only one set of ethernet pins.
<hno> hi panda84kde
<hno> oliv3r, yes it's a bit stilly. gmac can do 10/100/1000. emac can barely do 10/100..
<panda84kde> I've hear from the KDE / PA / Vivaldi guys that A10/A20 are among the most Free Software friendly. I've heard that the only binary part used is the GPU 3D blob, but that even that might be eventually replaceable with lima driver. Are there things more or less true?
<mripard_> the GMAC and EMAC don't appear to be pin-compatible, that might explain
<oliv3r> i wonder if the gmac can work with a 100 mbit PHY
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<oliv3r> afaik rmii is backwards compatible with PHY
<oliv3r> er MII*
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<oliv3r> so a gmac driver, could work with both the old and the new PHY's but uses a differnt networking IP
<oliv3r> e.g. cubie2 should/could work much better with the new gmac hardware
<oliv3r> interesting concept :)
<oliv3r> anyway, editing the memory map wiki page to fill in th eblank
<hno> oliv3r, there is still many blocks not documented in the manual.
<oliv3r> yeah :(
<oliv3r> allready saw :(
<oliv3r> why, WHY!
<hno> but they are getting fewer with each release.
<hno> why? Because they do not have any digestable manuals most likely.
<oliv3r> yeah i know
<oliv3r> well some sections they delibertaly remove
<hno> or because it's not AW blocks.
<oliv3r> that's most likly the case
<hno> i.e. GPS block is all third party.
<oliv3r> how do SPI and USB relate?
<hno> what do you mean?
<hno> SPI is a syncronus serial protocol with no standard beond 4 documented & incompatible signalling modes.
<oliv3r> the wiki says SPI0 (USB OTG)
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<hno> USB is an asyncronous serial protocol with a standards body documenting every bit.
<hno> oliv3r, someone made a typo.
<oliv3r> a big one at that
<oliv3r> but no relation, what I thought; but maybe I missed something :)
<hno> oliv3r, it's you :)
<oliv3r> noway!
<oliv3r> it must have been me! history does not lie
<oliv3r> i guess i added it to the wrong section :S
<hno> yes
<oliv3r> but its fixed :)
<oliv3r> btw, we also have a HDMI1 register, 128kb
<oliv3r> my guess, it's for the CEC/Networking stuff that's in the 1.4 spec
<hno> There have always been a HDMI register block.
<arokux> what ccu and ccmu stand for? clocks unit, clocks management unit? :$
<hno> but not so large.
<hno> something like that.
<oliv3r> hno: the other one still exists
<oliv3r> i think 1 is for the 'dvi' bit and this one for the additional stuff
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<hno> it looks like the A20 also have secure boot...
<oliv3r> arokux: clock control module/unit
<oliv3r> hno: haven't found that yet, but if they use 'trustzone' for that, figures
<hno> not trustzone. Only SS and SID.
<oliv3r> so how do they use secureboot?
<hno> but a working trustzone requires a working secure boot.
<oliv3r> i thought secureboot was that the BROM checks the signature of the SPL and only boots that (etc etc)
<hno> you set store a boot encryption key in SID, and BROM uses SS to decode.
<hno> and keys locked away from CPU access.
<oliv3r> ok, maks sense
<oliv3r> but we can read the SID?
<oliv3r> so sign our stuff using the sid?
<hno> not if locked.
<oliv3r> unless that's the reason we read it back as blank
<oliv3r> if the BROM can read it, 'so can we'
<oliv3r> using fel mode at the least i'd hope ;)
<wingrime> oliv3r: we shold se brom dissasembly
<oliv3r> wingrime: yeah that's what I mean, if the brom can read it, and we have the brom binary, we should be able to figure out how to unlock the SID and read it back
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<wingrime> oliv3r: not simple, for example on intel cpu, some bits can be "locked" writing special bit, after that you can trow but back
<wingrime> *you can't trow bit back
<oliv3r> 'cpu configuration register' :)
<oliv3r> wingrime: but if the BROM HAS to read the SID to decrypt the bootloader
<oliv3r> the BROM needs to be able to read the SID
<oliv3r> if the BROM can read the sid
<oliv3r> so can we
<wingrime> oliv3r: after read and decript brom can set such bit, and it will be unpossible re-activate it latter (except reset glitch)
<oliv3r> wingrime: but what if we force the chip into FEL mode
<hno> oliv3r, the BROM can't read it if locked. SS uses it directly from SID: See bottom of page 221.
<oliv3r> hno: ahhhh, is that new in a20 manual?
<oliv3r> i'm not that far, doing the wiki dance atm :)
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<oliv3r> in that case, yeah, we could potentially get fucked :p
<wingrime> oliv3r: where new man?
<hno> oliv3r, yes, both SID and SS differs noticeably from sun[45]i.
<wingrime> hno: SID can something new?
<wingrime> and SS?
<hno> it's quite likely possible to read the SID if programming voltage is applied, but unsure if it's possible to get into the execution of locked down CPU.
<hno> wingrime, SS can do encryption as before. New is that it can use key from SID.
<hno> SID is larger than before and can be locked so the CPU can't read parts, and BROM supports encrypted boot with locked keys.
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<hno> Haven't looked into the BROM details, only A20 manual.
<wingrime> hno: are you sure thats new ? I see "1: Select SID_RKEYx from Security ID
<wingrime> in 13 man
<wingrime> *a13 man
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<oliv3r> mripard_: cpucfg reg is used on a20 for hotplugging etc of the CPU
<wingrime> oliv3r: oh, man in dl
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<oliv3r> well our sids on the A20's we have so far are all blank
<oliv3r> or locked :p
<oliv3r> wingrime: yep :)
<oliv3r> wingrime: so SS could use SID in a13 allready?
<oliv3r> then it's quite likly it could do the same in a10
<oliv3r> i wonder if we can extract keys using the SS
<wingrime> oliv3r: a10 have no sid and ss in man so yes
<mripard_> oliv3r: yeah, I know.
<oliv3r> oh :(
<oliv3r> it's used for SMP stuff I take it?
<wingrime> oliv3r: do you saw Smart Card Reader
<oliv3r> we had that in A10; it was called SCR :)
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<wingrime> oliv3r: now we have regs in a20 man
<oliv3r> i also saw that PS/2 is bi-directional, as in it can work as client OR host
<oliv3r> wingrime: haven't looked that far, filling in the memory map atm
<wingrime> 0_0 PS/2 regs
<oliv3r> we had those i think
<oliv3r> or atleast a driver if i'm not mistaken
<oliv3r> but you can use the a* to emulate a keyboard/mouse :p
<wingrime> oliv3r: ps/2 mostly useless when you have gpio
<wingrime> oliv3r: it easy to emulate
<oliv3r> yeah but if you have it in hardware, might aswell use it
<oliv3r> saves you from writing a bitbang driver
<oliv3r> twi3 is new for a20
<oliv3r> but a10 had the register space
<oliv3r> it's like they didn't add it to the pinmuxes
<oliv3r> or, maybe its there but nobody knew about it
<rm> would be nice to use some old PS/2 mice and keyboards :)
<rm> and save the few USB ports
<oliv3r> i agree, i think the cubie even brings out 1 port
<oliv3r> besides, I find ps/2 far more reliable
<oliv3r> (if you don't hotplug it)
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<wingrime> oliv3r: take a look at new sid
<wingrime> oliv3r: it now can store more keys
<oliv3r> nice, but we can't write to it anyway :)
<oliv3r> but it'll be good to adapt my driver to it :)
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<wingrime> When JTAG key read lock flag is off, the 64-bits JKEY value can
<wingrime> be read out by CPU, else it is undefined.
<oliv3r> hmm?
<wingrime> 0: HDMI key HDCP value c can keybe read read lock out flag by CPU
<wingrime> 1: key value e can’t be read out by CPU
<oliv3r> ??
<oliv3r> hdcp uses the SID too?
<oliv3r> probably via the crypto engine
<wingrime> oliv3r: we now have more keys in it
<wingrime> oliv3r: we now have JTAG,BOOT, HDCP keys
<wingrime> 0: Boot key key value read can lock be flag read out by CPU
<wingrime> l 1: key value can’t be read out by CPU
<wingrime> oliv3r: I was right it have read lock flags
<hno> oliv3r, SID writing is documented.
<oliv3r> hno: oh! ok i will read that first :)
<ganbold> hm, does same driver for usb ehci work on cubie2/A20?
<oliv3r> if it's writeable it might be readable the same way; but even so, we can modify it to sign our own stuff if needed (assuming the pins are accesable
<oliv3r> ganbold: very likly
<hno> oliv3r, was documented in A13 as well, but looked like A13 manual had wrong register offsets. A20 SID is different.
<hno> well, not in function but in register offsets, and more functionality.
<oliv3r> gps is 64k
<oliv3r> that's one big register
<hno> GPS is a big black proprietary blob hole.
<oliv3r> aye
<hno> but maybe we could get some of the open GPS hackers onboard and do something about that.
<oliv3r> aye
<oliv3r> replicant developers should have _some_ expertise there
<oliv3r> but need a way to connect hardware
<hno> Need to check if Olimex A20 board have GPS pins routed. I think so.
<wingrime> Video Engine (Phoenix 3.0)
<oliv3r> gmac is also 64k register blob?!
<oliv3r> hno: i think they routed everything
<oliv3r> wingrime: yeah i posted that: ) we know the name of the VE :)
<hno> oliv3r, yes I know, but better verify before trying to drag in GPS people.
<hno> replicant is doing GPS hardware? Most people are only talking to complete GPS modules.
<rellla> oliv3r, wingrime: isn't there cedarx used in a20?
<oliv3r> hno: i know they try to reverse the gps on the S2
<oliv3r> rellla: cedar is called 'phoenix 3.0' in a20
<oliv3r> so i guess the previous editions are called pheonix 2.0 and 1.0 :)
<oliv3r> A20 has a high-speed timer
<oliv3r> maybe a10 has it too
<mripard_> no
<mripard_> A10 is the only one that doesn't have it
<hno> oliv3r, any reference?
<oliv3r> a13 has it too?
<mripard_> oliv3r: yep
<wingrime> why Phoenix 3.0 ?
<wingrime> it was cedarX
<wingrime> audio engine still in place
<oliv3r> sun5i calls it 'sync timer'
<wingrime> but that we can dts and ac3 undocumented in a20
<oliv3r> wingrime: maybe that's the name of the IP
<hno> A10 have at least one high speed timer.
<oliv3r> hno: the hstimer in a20? 1c6000-1c60fff
<hno> probably not that.
<mripard_> hno: you mean the 64 bit counter ?
<hno> probably. was long since I looked at these things.
<oliv3r> what could "GIC" stand for?
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<oliv3r> 32k worht of registers
<hno> interrupt controller.
<mripard_> oliv3r: ARM`s Generic Interrupt Controller
<hno> ARM IP block. Well documented.
<oliv3r> but interrupt is allready defined as a 1k blok at 1c20400
<oliv3r> do they have both interrupt controllers in there now?
<hno> oliv3r, there is never only one interrupt controller...
<oliv3r> a10 only documented the one, 1k worth of registers ;)
<oliv3r> this one is huge!
<mripard_> yeah, the GIC has a lot of features.
<oliv3r> so it looks like they left the old one inthere too
<oliv3r> probably doesn't work
<mripard_> or they just forgot to remove it from the memory mapping
<wingrime> mripard_: looks like we have normal reset documented in a20 man
<oliv3r> a20 is resettable?
<oliv3r> god you people are horrible!
<oliv3r> defouring the manual like beasts
<prite> We have a sunxi tablet with an Elan eKTF touchscreen. No official driver source is available, but we found a reverse engineered patch that didn't work too well on Ubuntu.
<prite> We have now fixed the patch to work on Ubuntu as well as Android. Any considerations before we submit it for merging into sunxi-3.0 tree?
<oliv3r> port it to sun-3.4 :)
<oliv3r> we are trying to depreciate the 3.0 tree
<prite> We would love to use a new(er) kernel! Unfortunately, the patch itself was for 3.0. Will see what we can do.
<oliv3r> shouldn't be hugly different
<prite> Btw, when is sun-3.4 slated to be released?
<oliv3r> prite: who is 'we'?
<oliv3r> about a year ago?
<mripard_> wingrime: where ?
<mripard_> CPU configuration?
<oliv3r> the reset framework
<oliv3r> :D
<oliv3r> oh exciting things
<prite> oliv3r: 'We' is India's low-cost tablet dev. team. #Aakash
<oliv3r> prite: ahhh, awesome
<hno> mripard_, there is one RESET per CPU. Only resets the CPU. Used for hot plug I think.
<wingrime> mripard_: yes per core
<oliv3r> must be cpu config then
<oliv3r> watchdog is probably simpler ;)
<hno> watchdog resets it all.
<oliv3r> CPU Build In Selft Test has its register defined at least
<wingrime> mripard_: read a20 manuak, thre new stuff for smp here
<wingrime> oliv3r: we have TV encoder registers
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<hno> wingrime, TV encoder documented now?
<wingrime> hno: yes
<hno> that is the TV-out? Or in?
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* hno guesses -out
<wingrime> out
<wingrime> as DACs on diagramm
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<hno> Wasn't that documented before? Or only source code?
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<wingrime> also usb documented for a20
<oliv3r> Encoder is is OUT, Decoder is IN
<oliv3r> wingrime: REALLY?
<oliv3r> wingrime: we know that there's 4 encoder dacs that are used for VGA (RGB) composite etc etc (see fex guide)
<oliv3r> anybody have an idea what the AVG modul is? it's the last 128k block beforecoresight debug
<oliv3r> a13 doesn't seem to have it
<Black_Horseman> companieros adios
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<oliv3r> not used in the code however at all
<oliv3r> it's defined in platform.h; and that's it
<oliv3r> Automatic Voltage Gain is what makes me think
<wingrime> oliv3r: most intersting how much undocumented crap we have
<oliv3r> still yes
<oliv3r> but ti's getting better
<panda84kde> hi guys. Has Mali400 binary dirver been tested on A20 or only on A10?
<oliv3r> i think only a10
<panda84kde> Is there any blocker on A20 (e.g. missing kernel modules) or should it work the same?
<oliv3r> no clue afaik
<oliv3r> but not much imo
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<oliv3r> ok wiki page has been exapnded
<panda84kde> BTW I see SATA is not listed for A20, but it's supported. Can I update the main page?
<oliv3r> sure
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<oliv3r> there's more counters too, each CPU has its own counter hooked up to the 24M and 32k oscillators
<oliv3r> a20 manual even has a nice clock tree diagram :)
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<oliv3r> i'm telling you, HDMI1 'block' is cec etc, it's probably some microcontroller-like thing that handles CEC and network (i doubt they do networking even though that's in the 1.4 spec)
<wingrime> mripard_: sun6i use GIC?
<oliv3r> wingrime: yes
<oliv3r> says hdmi is 1.4 even on a10
<oliv3r> 1.4 added HEC (100mbit hdmi ethernet connection)
<oliv3r> so CEC, HEC, ARC (audio return channel). interestingly HEC runs over pin14; did not know this, thought CEC and HEC shared the same pin
<oliv3r> pin 14 + pin 19*
<oliv3r> wonder how they are pushing 100 mbit over just the 1 pair. 10mbit sure, no problem, i thought 100mbit requried 2 pairs
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<wingrime> oliv3r: hdmi - one way channel
<wingrime> oliv3r: so one twist enought for simplex conection
<oliv3r> wingrime: nonon
<oliv3r> HEC is HDMI Ethernet
<oliv3r> but i bet it's 100Mbit halfduplex
<oliv3r> normally you have 1 pair for TX, 1 pair for RX (10 OR 100mbit appearantly)
<oliv3r> so if it's half duplex, you have one pair only that's required
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<oliv3r> i see gmac clock register, i wonder if we ever had emac clock register
<oliv3r> Turl: how is the emac clocked on a10? since a20 has gmac clock register seperated
<oliv3r> oh interestingly, the gmac clk register, configures the PHY as MII or RGMII
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<wingrime> oliv3r: I not sure we need IR driver
<oliv3r> i need it :p
<oliv3r> for setop box ;)
<wingrime> oliv3r: I find that mainline have gpio-ir
<oliv3r> but i'll do unification after reading a20
<oliv3r> yeah but i will use a mele m5
<oliv3r> which has remote + sensor
<oliv3r> so not gonna rewire it to gpio :)
<wingrime> oliv3r: you not realy need
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<oliv3r> tell that to my gf
<oliv3r> 'sweety, you don't need a remote'
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<wingrime> oliv3r: you realy not understand at all :((((
<wingrime> oliv3r: we can use gpio-ir-recv.c
<oliv3r> you want to reconfure the IR0 pin as gpio :p
<wingrime> oliv3r: that in mainline
<oliv3r> a workaround :p
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<wingrime> oliv3r: IR0 are multipexed with GPIO
<wingrime> oliv3r: so you not realy need IR controller for low speed transfers
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<wingrime> oliv3r: can ou try add { .compatible = "gpio-ir-receiver", },
<wingrime> to dt
<wingrime> ?
<wingrime> mripard_: ping
<mripard_> pong
<oliv3r> wingrime: yeah, i'll write an IR driver for it then :)
<oliv3r> if we have hardware, why not use it
<mripard_> almost leaving though
<wingrime> Documentation/devicetree/bindings/media/gpio-ir-receiver.txt
<oliv3r> no point in burdening the CPU :)
<wingrime> oliv3r: you need burdening anyway
<wingrime> oliv3r: check code
<oliv3r> lol
<oliv3r> probably
<oliv3r> ohh!
<oliv3r> a20 has documented reg 0x24
<oliv3r> its called 'VERSION REGISTER'
<wingrime> ?
<oliv3r> read-onyl
<wingrime> mripard_: Documentation/devicetree/bindings/media/gpio-ir-receiver.txt
<mripard_> yes, what about it?
<wingrime> mripard_: we have ready to go gpio ir reciver driver
<oliv3r> hno: there's more info in the a20 sram section then we figured out so far
<wingrime> mripard_: and IR0 port can be muxed with gpio
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<wingrime> mripard_: so It possible that driver will work on cb without any change
<wingrime> mripard_: what do you think about ?
<mripard_> wingrime: are you sure it's compatible?
<wingrime> mripard_: I will check soon
<mripard_> nah, we can't use it
<mripard_> it uses a GPIO interrupt
<mripard_> and there's no EINT on the IR0 pins
<wingrime> mripard_: are you sure
<oliv3r> and we have hardware IP; either use it, or not
<oliv3r> using GPIO-ir is a hack (for devices that don't hae an IR receiver in hardware)
<wingrime> mripard_: PB4
<wingrime> mripard_: PB4 when not muxed to IR
<oliv3r> does pb4 have an intterupt? you need an interrupt for the GPIO ir
<wingrime> oliv3r: that IP useful not for RC
<wingrime> oliv3r: if for normal two direction IrDA
<oliv3r> but all settop boxes use that IP for RC :)
<wingrime> mripard_: ?
<wingrime> mripard_: there is irq for PB4?
<wingrime> oliv3r: gpio with irq will have same preformace than gpio with such speed of RC
<oliv3r> page 100 is really interesting of manual
<oliv3r> pwm in a20 is the same as a31
<oliv3r> and much less prescaler values
<oliv3r> hmm maybe more
<oliv3r> have to see
<wingrime> mripard_: ??
<oliv3r> i thinkk hes gone :p
<oliv3r> did we have SJTAG registers before?>
<oliv3r> nope we didn't
<oliv3r> A20 manual has jtag registers
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<mripard_> wingrime: yes, I'm sure that PB4 has no interrupt on it.
<oliv3r> mripard_: SID on A20 is a little different, much larger mostly
<oliv3r> there's now info about writing it aswell
<mripard_> oliv3r: yes, and with 3 banks right?
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<wingrime> mripard_: stange , i thinked that every port can be EIRQ on sunxi
<oliv3r> i suppose if you call them that, it's split up into sections, root key, boot key and jtag key
<mripard_> wingrime: nope, only a few of them
<oliv3r> mripard_: but you might aswell call it 1 big key
<oliv3r> mripard_: so in terms of sysfs, 1 eeprom entry, then 1 entry for each key?
<oliv3r> oh and half a 'custom key'
<mripard_> oliv3r: nah, I wouldn't do such thing
<mripard_> either one instance with everything
<mripard_> or a few smaller instances
<Turl> mripard_: it's nice to have AW people that can come out of the blue and clarify stuff :)
<mripard_> Turl: yep :)
<oliv3r> anyway, not sure how to let the driver know what configuration to use, i should check your i2c patch I suppose :)
<Turl> mripard_: just noticed when viewing in tb that they used html email :p
<oliv3r> lkaml?
<oliv3r> lakml*
<Turl> oliv3r: emac... check dt? :P I dunno if we're missing any clocks on it
<oliv3r> well i didn't see anything in the docs about it
<mripard_> oliv3r: "what configuration to use" ?
<oliv3r> what register mappings/sizes
<oliv3r> sun7i has more registers, thus different mappings
<mripard_> I'd take whatever comes from reg
<mripard_> you already provide the size there
<mripard_> ah, but there's the few extra registers
<oliv3r> but i thought you wanted the size to be 1k as the manual specificies it as 1 k
<oliv3r> yeah
<mripard_> yeah, look at the i2c patches then :)
<oliv3r> the only thing i can think of is to read the compatibility name :)
<oliv3r> yeah i thought of that too
<oliv3r> the old ones that is
<oliv3r> or no, the new marvel ones
<hno> Turl, AW said something public?
<oliv3r> not the first time :)
<oliv3r> Turl: what's the title of the mail in question? :)
<Turl> hno: AW people sometimes drop a (pair of HTML) lines on lakml when we doubt documentation or such
<Turl> oliv3r: sec
<hno> Turl, good to know they monitor progress.
<Turl> oliv3r: "Re: Re: [PATCH 4/4] ARM: sun6i: Enable clock support in the DTSI" on lakml
<wingrime> Turl: link please
<hno> Turl, any archive of that? I only find discussion between mripard_ and Emilio López
<oliv3r> same
<oliv3r> looking for it aswell
<oliv3r> don't see it on gmane's ntp-thread either
<Turl> well, I was in To, I can see the lists on Cc
<Turl> maybe the servers dropped the mail, it was HTML
<oliv3r> very likly
<Turl> I cannot find it on or spinics for linux-arm
<Turl> hno: that other guy is me btw :)
<hno> suspected so.
<oliv3r> save way to get messags to people without being publically logged on a ML :p just write in html
<oliv3r> you can always reply in txt and say 'oh thank you'
<oliv3r> that way, it'll be logged! >: )
<hno> yes, using HTML mail is a good way to make sure the community have a hard time seeing you.
<Turl> hno: btw, does uboot select internal/external losc?
<wingrime> oliv3r: a31 have 912 Mhz clocks too?
<oliv3r> wingrime: no idea, i don't have a31 hardware
<oliv3r> PA is emac and GMAC
<oliv3r> pins look compatible (which makes sense
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<oliv3r> lol
<oliv3r> :D
<oliv3r> pff, i even knew that from the old datasheets!
<oliv3r> but ti's nice that they clarify things
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<Turl> wb hipboi
<oliv3r> hipboi: thank you for getting the a20 manual; it's very very usefull :)
<Turl> oliv3r: you've got an a20 manual? :O
<Turl> 835 pages, cool :)
<hipboi> Turl, :)
<oliv3r> Turl: :D
<oliv3r> why do you think we've been so busy today talking about a20 :D
<Turl> :P
<oliv3r> but it looks like, a20 has both emac AND gmac
<oliv3r> on same pins, but still
<Turl> now I just need the damn customs to release my cubie already :p
<wingrime> hipboi: thanks,
<oliv3r> so emac problems could remain the same unless we use the new gmac code
<oliv3r> Turl: yeah! excitement ensures!
<oliv3r> i'm thinking of getting a a20 hdmi stick; just for the hell of it
<oliv3r> though i should get an mele m5
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<Turl> oliv3r: they even included a glossary so you can understand cryptic acronyms :D
<oliv3r> lol aye
<oliv3r> Turl: go read; i've added some preliminary stuff allready to the wiki :)
<oliv3r> it also fills in more blanks
<wingrime> oliv3r: at least SRAM version reg covered
<Turl> oliv3r: no sata docs :(
<oliv3r> looks like a20 may have dropped pata
<oliv3r> wingrime: aye
<oliv3r> PH MUX3 was pata; it's now: 'erxd3'
<Turl> oliv3r: it even has a smart card reader :o
<oliv3r> a10 had it too
<oliv3r> we just dindt knwo what it was
<oliv3r> 'SCR" it was called before
<oliv3r> wrong paste
<wingrime> oliv3r: PATA still on map
<Turl> oliv3r: nice, PS2 docs :)
<oliv3r> FOUR hs timers on A20
<Turl> and IR docs, not sure if we had those
<oliv3r> Turl: i didn't know a10 was missing them, but ps/2 is something i wanted to play with as it should be relativly simple
<wingrime> Turl: also , SmartCard
<oliv3r> Turl: yes we had IR docs, but i don't see PS/2 docs
<oliv3r> damnit
<wingrime> Turl: oliv3r: hno: have any idea what IIS-[012]
<oliv3r> oh come on
<oliv3r> wingrime: yeah
<oliv3r> I^2S
<oliv3r> Sound :) check memory map
<oliv3r> it's like i2c (twi) but for sound
<Turl> oliv3r: look for "PS2"
<oliv3r> in the old docs? i don't see it in a10 or a13 manuals
<Turl> oliv3r: in the A20 ones
<oliv3r> what iw anted to paste 'for details about GIC, visit arm GIC PL400'
<oliv3r> very cool
<oliv3r> i'm at the GIC section; i'll find it ;)
<Turl> oliv3r: they expanded SID to hold a jtag key and hdmi key now :p
<oliv3r> funny how the security system has the 'DIE BONDING ID'
<oliv3r> Turl: and a custom key and a 'boot key'
<oliv3r> and the security unit can read it
<oliv3r> without intervention of the PCU
<oliv3r> "secure boot"
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<oliv3r> no dram docs
<wingrime> no cedarV and cedarA
<wingrime> no sata
<wingrime> no pata
<oliv3r> flash info is like from a31, so a little more detailed
<oliv3r> pata is gone i think
<oliv3r> they removed it from the soc
<wingrime> oliv3r: pata on a20 map
<oliv3r> not in PIO/mux list
<wingrime> oliv3r: also don't forget about ACE
<oliv3r> it's still there afaik
<oliv3r> but we have zero docs for it
<oliv3r> mmc docs still missing
<wingrime> oliv3r: where that html drop?
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<oliv3r> wingrime: html drop?
<wingrime> oliv3r: mail or something
<oliv3r> ohh allwinner employes responded on the mailing list (but in html)
<oliv3r> Turl: reached PS2 :p
<oliv3r> Turl: also it's funy that it's a device AND host dual role controller
<oliv3r> so i think you can use a ps2 for input OR emulate a mouse/keyboard when you connect it to a pc :)
<oliv3r> the way that reads, it looks like they bought the IP
<oliv3r> 'can be integrated with AMBA bus'
<oliv3r> nice, but sunxi doesn't have amba bus in that sense, they call it APB bus
<oliv3r> so why list that? 'comply with AMBA spec rev 2.0'
<oliv3r> 'for easy integration into SoC'
<wingrime> AMBA are opensource
<oliv3r> yeah sure, but this contorller is IN their soc
<wingrime> on opencores
<oliv3r> why mention it?
<oliv3r> ah
<wingrime> opencores
<oliv3r> good point
<oliv3r> maybe they got the PS2 IP from opencores ;)
<wingrime> opencores can GPLize whole chip in somecases
<oliv3r> LOL that would be to funy
<oliv3r> 'allwinner, you are using this GPLed blob in your core, you are infringing
<oliv3r> release Vhdl to your soc :)
<oliv3r> but seriously, i would not be supprised if cedarV/A infringes
<arokux1> hi guys
<oliv3r> not supprised at all
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<ssvb> oliv3r: the L2 cache configuration was pretty clear based on running benchmarking tools, but it's good to have it confirmed :)
<oliv3r> aye ;)
<Tsvetan> A20 have 8 UARTs did someone here even succeed to enable one more than UART0?
<ssvb> oliv3r: does A20 have some sort of a temperature sensor?
<oliv3r> we have USB OTG registers!
<oliv3r> ssvb: in theory, yes
<oliv3r> the same as A10 has
<Tsvetan> seems all these UARTs are multiplexed with Ethernet etc so you cant use them
<oliv3r> Tsvetan: hasn't it always been that way?
<ssvb> oliv3r: hmm, do we have a driver for it to read the temperature?
<Tsvetan> oliv3r I have no idea
<oliv3r> PA does UART1 and UART2
<Tsvetan> but muxed with Ethernet
<oliv3r> ssvb: the register never gave me anything usefull
<oliv3r> Tsvetan: yep
<ssvb> oliv3r: :)
<Tsvetan> so there are 7 UARTs which cant be used at all :)
<oliv3r> Tsvetan: but PI mux 3 does also UART2
<oliv3r> Tsvetan: only UART1 is muxed with ethernet
<oliv3r> uart2 is the other one and has an alternative mux
<oliv3r> ssvb: the code has it all commented, but there are signs it was tried
<Tsvetan> oliver according to allwinner if you enable Ethernet you lose UART1,2
<Tsvetan> no matter that they go to different ports
<oliv3r> ssvb: if you look at a20 manual page 209: register 0x20 :)
<oliv3r> you loose their primary mux, uart2 is muxed to PI
<oliv3r> but that's shared with SPI1
<oliv3r> Tsvetan: that's new, normally if you can mux it to some other pin, it's fien
<Tsvetan> it may be communication problem between me and allwinner Im not always sure they understand me :)
<Tsvetan> hipboi what do you say? how many UARTs can be used in A20 if you use Ethernet, SATA etc?
<oliv3r> Tsvetan: i hope that's the case, because if not, then there's some special magic at work invalidating IP cores :)
<Tsvetan> lets see what hipboi will say at least he know chinese :)))
<oliv3r> hahaha, yeah
<oliv3r> arokux1: we have USB register documentation in the A20 manual
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<arokux1> oliv3r, oh, nice.
<oliv3r> arokux1: and EHCI and OHCI register information
<oliv3r> chances are that this is also bought IP, and i wouldn't be supprised if its' from the same source
<oliv3r> documetnation for OTG and HOST is different, so it looks like only host + ps2 is from same vendor
<arokux1> oliv3r, and where is the documentation? I don't see it on the
<oliv3r> I2S also same vendor
<arokux1> oliv3r, can I put a reference to it on the wiki page?
<oliv3r> Turl: 16 kiB SRAM is split for TX and RX; 3k is for TX, 13k is for RX
<oliv3r> arokux1: sure :)
<oliv3r> but it might get decrypted so name might change
<oliv3r> i'd link to the generally
<arokux1> oliv3r, wow, 835 pages. a gift from allwinner?
<oliv3r> a little bit of emac info, we never had that either, so i really think emac AND gmac IP cores are available
<oliv3r> arokux1: a10/a13 manuals are bigger :)
<oliv3r> i lie
<Turl> oliv3r: no, they're half the size :p
<arokux1> a10 is much smaller
<arokux1> if they were half......
<oliv3r> Turl: the manual says 3k tx; 13k rx; but i wouldn't be supprised you can do it anyway you want
<oliv3r> arokux1: it is half
<oliv3r> Turl: ohh the manual
<oliv3r> Turl: sram! sram! stay on topic
<Turl> arokux1: 495 for A10 & 409 for A13
<Turl> oliv3r: what about it? :P we have known that for some time right?
<oliv3r> which means, a20 can use either/or driver with either/or PHY and thus the emac bugs can be ignored :)
<oliv3r> Turl: you said sram was for rx only
<Turl> oliv3r: eh?
<oliv3r> a few days ago
<oliv3r> when you where playing with the sram driver
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<Turl> I can copy code just fine so you can "tx" too :p
<arokux1> Turl, oliv3r you are right, sorry, I've used data sheet so far!
<oliv3r> 16k jumbo frames support on the gmac
<Turl> oliv3r: ah, I think you're confusing what I said
<oliv3r> doesn't say if its connected to sram at all
<Turl> oliv3r: I was talking about emac, and said dma was used for tx only on the driver we have
<oliv3r> ohhh possible
<oliv3r> zero register information on gmac driver
<oliv3r> :(
<arokux1> stupid me :(
<oliv3r> gotta find out which IP they are using
<arokux1> oliv3r, are the docs a gift from allwinner?
<oliv3r> but we have sun6i gmac driver :)
<oliv3r> arokux1: leaked
<arokux1> oliv3r, :)
<oliv3r> so dunno how much they are gifted; though a20 manual is via hipboi
<arokux1> oliv3r, thanks a lot for this pointer. I had only a fraction of this info!
<oliv3r> woprr: great, i see in the a20 manual that transport stream control and status registers are ... empty.
<oliv3r> the control register has 2 bits atleast described in the cubieboard a10 doc
<arokux1> oliv3r, question: is dropping of the code welcomed in sunxi-4.0 if it is unused, or it should stay there just in case it could be useful later?
<oliv3r> sunxi-3.0 will be depreciated hopefulyl soon
<oliv3r> hno we have SOME can bus info now too
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<oliv3r> Turl: omg they got their own glassary wrong
<oliv3r> afaik, AVS for allwiner, is the Audio Video Sync timer
<oliv3r> they call it 'Audio Video Standard, a compression standard for digital audio and video'
<oliv3r> lolol
<woprr> oliv3r, ack
<oliv3r> ssvb: nice, DEFE contains a de-interlacer
<ssvb> oliv3r: good :)
<oliv3r> ssvb: can you use that as a seperate thing?
<oliv3r> i mean, can I decode some video, have the DEFE de-interlace it?
<oliv3r> or is it for the enitre output stage
<oliv3r> e.g. can I deinterlace a single layer
<oliv3r> it looks like it can take whatever is on the memory bus (mbus) and deinterlace it and offer it to the DEBE
<ssvb> oliv3r: we are reading the same docs, I guess the writeback feature should allow to do this without sending anything to the display if you mean that
<oliv3r> ssvb: you reading a20 aswell? :)
<ssvb> oliv3r: not yet, just remember this from the a13 manual
<oliv3r> ssvb: well i'm just curious, a lot of braodcast material is still interlaced (god knows) and doing it in software is almost impossible on a10/20
<oliv3r> i know my htpc has real trouble with most methods
<oliv3r> so i wanna know if we can offload it
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<oliv3r> ohhh yes, you can read from memory, make it go through the scaler, the vpp, the csc and then either output it back to memory OR to the DEBE
<ssvb> oliv3r: the output of cedar is also tiled, which may make it more difficult for post-processing, that's why I looked into it a bit
<ssvb> oliv3r: having a feature complete vdpau would be nice
<oliv3r> that's what i'm thinking ;)
<oliv3r> so while i'm not sure on all the lingo and all possible methods
<oliv3r> if cedar is tiled, how is that a big problem? won't we have a full frame in memory at some point?
<oliv3r> and can't we thus de-interlace the full frame?
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<oliv3r> also i always thought the front-end would be the output bits but i see now that its the other way around, the 'backend' is what gets sent to display eventually
<ssvb> oliv3r: if the output is tiled in memory (32x32 blocks), then it's difficult to do anything with it using g2d
<oliv3r> ah, so we don't have full frames in memory?
<oliv3r> ever?
<oliv3r> anyway, i don't even think we need the write back channel for that
<oliv3r> the DEFE has an 'output select' which either goes to DEBE OR back to memory
<oliv3r> (from the block diagram)
<ssvb> oliv3r: as far as I know, g2d does not support tiled formats natively, this makes it a bit tricky
<oliv3r> thats stupid :S
<oliv3r> ok we'll see when we reach that bridge
<ssvb> oliv3r: we have full frames in memory, but the pixels are just rearranged a bit
<oliv3r> spent 3 hours going over the manual :) forgot to do tons of stuff now
<ssvb> oliv3r: it's probably not stupid if g2d is a third-party IP :)
<oliv3r> ssvb: now, is that upto cedarX the lib, or cedarX the IP
<oliv3r> e.g. is it fixable in any way?
<ssvb> oliv3r: defe supports tiled formats as input, cedarx produces tiled format as output, at least there is no problem when these two are working together
<oliv3r> well for de-interlacing, we don't need debe
<oliv3r> only defe, as it can put it back into memory
<oliv3r> i don't know how tiled deinterlacing affects image quality
<oliv3r> don't think it should be too bad
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<ssvb> libv: ping
<libv> ssvb: what's up?
<ssvb> libv: I have pushed dri2 tear free double buffering support
<libv> ok
<ssvb> also now it speaks the mali dri2 dialect, which may be incompatible with your lima code
<libv> right...
<libv> i already need to tell it to load the lima dri driver
<libv> i might try it out on my mele, which is currently geared for framebuffer mali binary, whereas my a7hd and odroid are geared for mesa bringup
<ssvb> I'll try to document all this stuff, just to make it clear how it works
<ssvb> one of the problems is that the normal xorg dri2 framework and the mali blob don't quite understand each other and this used to cause some issues
<libv> right
<libv> it's good that you're doing this work, and it might mean that X11 mali support finally gets somewhat acceptable
<ssvb> yes, a lot of people showed recently asking about Qt5, that's why this stuff had to be revisited
<ssvb> now Qt5 should work fine in X, though the framebuffer size has to be increased to allow it use double buffering
<ssvb> there needs to be enough space for two dri2 buffers in the offscreen area
<panda84kde> libv: here I am. I'll report to you if A20 works as A10 does as soon as I get my olinuxino A20. BTW, have you got any A20 board incoming?
<libv> no, but i do not intend to work on a20, i have a mali400mp4 which is fully supported by limare. mali400mp2 will just work
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<libv> ssvb: i see
<libv> ssvb: so now you can properly provide a qt5 cinematic experience which beats the libhybris hack hands down?
<ssvb> libv: almost, we need triple buffering to clearly beat it
<ssvb> libv: with just double buffering, we are limited to 30fps
<ssvb> libv: (for 1280x720 fullscreen mode)
<libv> oh, why is that?
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<panda84kde> libv: oh, nice. Is lima driver still very experimental or is it somehow testable for the brave?
<libv> is it that heavy an application?
<libv> that it cannot render a frame between vsync being reported and the new frame address taking effect?
<ssvb> libv: we have to wait until scanout switches to the next buffer before starting rendering to a new one
<ssvb> libv: *rendering to the old one
<libv> right
<libv> panda84kde: there is only limare, not lima driver.
<ssvb> libv: so it's ~50fps without vsync, and 30fps (one update per two frames) with vsync
<ssvb> libv: triple buffering (or even use more buffers) should help because we don't need to wait
<libv> ah, right, it cannot reach 60fps as is
<ssvb> libv: there is only one major inconvenience with triple buffering - we would need to suppress the crazy console spam from the mali blob
<panda84kde> libv: sorry, what do you mean by that? that only limare is testable?
<arokux1> oliv3r, question: is dropping of the code welcomed in sunxi-4.0 if it is unused, or should it stay there just in case?
<libv> ssvb: console spam?
<ssvb> libv: redirecting it to /dev/null kinda helps, but the end users are not going to appreciate this
<ssvb> libv: the "[EGL-X11] [2274] DETECTED ONLY ONE FRAMEBUFFER - FORCING A RESIZE" bla bla
<oliv3r> libv didn't you sign up for a cubieboard a20 a while back?
<libv> panda84kde: like pretty much everyone else who has been asking questions like you have since you joined, you have not been willing to understand that there is not a proper driver yet, and that this is the reason why you have not found any solid information on a proper driver so far
<libv> oliv3r: i should be focussing on lima, not on disp stuff or bringing up and hacking sunxi-mali
<libv> so getting an a20 will be a distraction
<arokux1> oliv3r, are you going to buy a bunch of cubieboards2?
<oliv3r> arokux1: there is no sunxi-4.0 so not sure what you mean; there's no 4.0 kernel
<oliv3r> arokux1: i got 1 dev board
<libv> so it is better to let someone else get one of the community cubieboards
<oliv3r> libv: nono, lima is good enough ;)
<oliv3r> but having an mp2 would be 'nice to have' no? :) for testing
<libv> oliv3r: i have an mp4
<oliv3r> libv: ah i thoguht you signed up and got a dev board from tom
<panda84kde> libv: I'll update linux-sunxi wiki, so that becomes clear. This doesn't tell me "there's no driver":
<oliv3r> no problem then
<oliv3r> *goes back hacking*
<libv> panda84kde: "This is a work in progress and not yet ready for general use."
<libv> panda84kde: seems good enough, for those who wish to read and grasp that sort of information
<libv> oliv3r: i told cwabbott to get one, not sure whether he actually did ask for one or not
<ssvb> panda84kde: are you one of the "I want to use Qt5" folks?
<panda84kde> libv: infact I've asked (kindly) "Is lima driver still very experimental or is it somehow testable for the brave?" 'For the brave' is pretty different from 'not for general use'. However I don't want to waste your time anymore. Have a nice day and good job!
<marzubus> Hey! so I got my kernel compiled for the MK802 with arduino and webcam support! finally! rover is looking much more complete now:
<marzubus> and front view:
<ssvb> panda84kde: you can compile and run lima demo applications and use the mali hardware, it's just not a fully compliant OpenGL ES driver yet
<ssvb> panda84kde: err, I mean not you, but the "brave ones" :)
<libv> panda84kde: sorry to burst your bubble like this, but i see your line of thinking/asking questions quite often, and i saw you coming a mile away.
<panda84kde> ssvb: nope. I'm not. I just wanted to help in testing with A20, but only if that's something you're interested into. If that's too early just ping when I can help you.
<ssvb> panda84kde: ok, sorry, I thought that you wanted to use Mali on A20 (possibly with the binary drivers) for something practical
<ssvb> panda84kde: but even if you are only interested in lima, the first step anyway would be to resolve the issues with the mali kernel driver
<oliv3r> libv: i do hope he did
<oliv3r> was a simple form to fill in :S
* ssvb is waiting for the dust to settle and a workable 3.4 kernel on A20 :)
<oliv3r> marzubus: mars explorer?
<ssvb> libv: btw, there is no dri2 support code in the lima repository yet?
<oliv3r> arokux1: what do you wish to drop from that? If you refine the usb driver, you basically replace it :)
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<libv> ssvb: nope
<arokux1> oliv3r, not much yet, some unused defines etc.
<libv> ssvb: fbdev has been suiting me quite well for limare
<oliv3r> arokux1: if you wish to improve usb hci on sunxi-3.4 just hack/add the files you want and send a patch to the ML when the time is ripe :)
<panda84kde> ssvb: Well. First of all I promise I'm not interested in Qt5 on Mali. :) Second: yes, I understood that lima driver (or "will be lima driver") is not usable, but if I can help with testing (I'm neither a total noob, nor a kernel hacker). Third: yes, I asked if anybody used the binary driver on the A20. As far as I can understand from sources on the internet Mali binary driver can run glmark2-es2. If that's not a question to
<panda84kde> ask here I'll just shut up.
<libv> ssvb: besides, i still haven't found out how to tell the windowsystem or dri2 that rendering is done, i know i get told by dri2 to flush rendering in mesa
<arokux1> oliv3r, ok, thanks
<libv> but then the return of this flush seems to trigger xcb copy region or a swapbuffers
<ssvb> libv: I believe it should know automatically that the rendering is done when you swap buffers
<libv> so i have to explicitly wait on the rendering being complete
<libv> ssvb: as just said, the only point where i get told to flush out the render, is also the point after which the buffer is displayed
<libv> i haven't understood how the intel driver would do this any better
<ssvb> is there any problem with the buffer being displayed?
<libv> driver->dri2_flush(); xcb_copy_region is the code i am seeing
<libv> no, but it enforces strict ordering
<libv> and completely beats the way the mali is built
<libv> i have a whole load of threaded code for handling job returns in limare
<libv> you build up a render, and then tell this threaded code to finalize it and then throw it to the kernel
<libv> as soon as the job is handed over the to jobhandling code, the main thread can continue and start building up the next frame
<libv> when the job returns, the fbdev driver gets told to flip, by one of the job handling threads
<libv> i see no possibility of doing something similar with X/dri2/mesa
<ssvb> r3p2 submits back buffer request for each buffer
<ssvb> buffer requests and buffer swaps may run out of order to some extent
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<libv> as i would need to be notified that the frame is complete, and i would need a means of telling the windowing system that rendering has completed and that the buffer content is valid
<libv> and all i have is dri2_flush, which is both of the above in one, which is severely suboptimal
<ssvb> when the buffer content is valid. you do swap (at least in the "mali dialect of dri2")
<libv> but perhaps i missed something, mesa is not the most transparent codebases
<ssvb> when you want to render a new frame, you do dri2 back buffer request
<ssvb> that said, mali looks rather broken, so this may be not correct for any other drivers
<libv> ssvb: when you want to start building up the rendering of a new frame, or when you want to finalize the frame you just built up and want to send it off to the hw?
<libv> "render a new frame" is not precise enough in this context :)
<ssvb> I'll just try to write something in a wiki page, and then we can discuss it again a bit later :)
<libv> ok
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<oliv3r> hipboi: hey, can you confirm/deny whether eth and uart2 are somehow linked other then pinmuxing?
<oliv3r> hipboi: e.g. if you configure pa as ethernet, can you still use UART2 via PI? (Uart1 doesn't have an alternative mux, so you loose that)
<arokux1> oliv3r, any idea why virtual addresses are defined and not used afterwards? (SW_VA_SRAM_BASE etc.)
<ssvb> panda84kde: the binary driver works on A10 and can run glmark2-es2, A20 is expected to be also fine after the mali kernel driver gets taken care of
<oliv3r> arokux1: because allwinner code is horribly sloppy?
<arokux1> oliv3r, :) when those VA become "active" anyway.. from user space?
<oliv3r> i don't know how the AW code 'works' but it's a big mess, so don't read to much into it
<ssvb> panda84kde: some people tried to compile the mali kernel driver for A20, but looks like they don't have what it takes to do this job properly
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<panda84kde> ssvb: Thanks. That clears out what I was look for. So if I got it right A10 has the mali and ump kernel module in the sunxi-3.4 brach, while there's not for A20
<panda84kde> *looking for
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<ssvb> panda84kde: yes, the sunxi-3.4 branch is evolving to get complete A20 support at the moment, we are just not there yet
<panda84kde> ssvb: that's because Allwinner released a A20 Android kernel, and not a Linux one? Is the original drop in another branch of the same repository?
<ssvb> panda84kde: there is also 3.3 kernel from allwinner, with something resembling the mali kernel driver in it, but the ones who tried could not make it work so far
<ssvb> panda84kde: for the start, we want r3p0 kernel driver to match the version of the available userland mali blob
<panda84kde> ssvb: so if I want to try you'd suggest to take sunxi-3.4 branch and then apply these over it?
<hno> panda84kde, Allwinner 3.3 kernel will work with mali blobs delivered in the same Android SDK. Not sure if there is Linux MALI blobs available for that kernel.
<ssvb> panda84kde: the sunxi-3.4 branch already has the mali kernel driver, it just needs to be updated to do correct initialization of mali resources for a20
<hno> full A20 Android SDK was posted by cubieboard and can be found at
<oliv3r> i read your mail just now about that :)
<oliv3r> the u-boot sources are the boot0/1/uboot chain ones, right?
<panda84kde> yeah. I just was thinking that what I told did not make sense if A10 works and the branch is the same :)
<oliv3r> so shouldn't be too exciting
<ssvb> panda84kde: the mali kernel driver has a number of configuration knobs which need to be set right
<hno> oliv3r, yes should be. Asked for it as the instructions earlier only pointed to a binary u-boot.bin blob
<oliv3r> aye, i'll take a quick look at it
<hno> and the SDK release is almost certainly the GPL violating one.
<oliv3r> have 7 minutes of work time left ;0
<hno> I have downloaded the tgz on the build server.
<hno> not unpacked yet.
<Tsvetan> hno which version of the SDK is this
<oliv3r> who is tekkaman ninja and how is that not hansg's work?
<oliv3r> Tsvetan: android version 4.2.2
<Tsvetan> Allwinner promised to send me SDK 2.0 for A20
<Tsvetan> but I dont know which android version is inside
<oliv3r> i'm downloading righ tnow, but its ays 9h togo
<oliv3r> it's about 5G
<Tsvetan> I open the link seems this is SDK 1.03
<Tsvetan> what we got first was 1.0
<wingrime> Tsvetan: where
<Tsvetan> wingrime where what?
<wingrime> Tsvetan: link
<hno> wingrime, see above.
<wingrime> Tsvetan: I intersted with ACE binaries
<Tsvetan> ACE?
<wingrime> Tsvetan: seems we have undocumented ac3 and dts audio hw decoder
<wingrime> Tsvetan: audio hw decoder
<wingrime> Tsvetan: on a20
<wingrime> Tsvetan: I saw only old blobs for sun3i
<Tsvetan> I will ask rz2k to replace the current A20-SDK 1.0 torrnent with A20-SDK 2.0 as soon as I get it from Allwinner
<Tsvetan> but this will probably happend after 18/08 as we leave in vacation
<Tsvetan> and the DVD will come in our office while we are on vacation
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<wingrime> Tsvetan: DVD over mail?
<Tsvetan> DHL
<wingrime> why not use ftps
<wingrime> oliv3r: ^
<Tsvetan> downloading from ftp in China takes longer than DHL
<wingrime> Tsvetan: android build system have "repo" tool witch enable use many sources for download, using many git repos
<wingrime> Tsvetan: better get google stuff form google git
<wingrime> Tsvetan: overlay must not be big
<deasy> Turl, usually it's my trollometer who explodes on the web
<Tsvetan> wingrime android is not our focus, I get these SDKs just to give to you guys so you can see if there is something valuable which could be used in linux-sunxi
<wingrime> Tsvetan: thanks
<wingrime> hno: bootloader sources constained something valuable that we don't know?
<hno> Tsvetan, any plans on shipping devices with Debian/Fedora instead of Android preinstalled?
<hno> wingrime, yes.
<hno> well, haven't looked at this release. Only the 1.0 release.
<Tsvetan> hno do we have GPL NAND packer?
<wingrime> hno: for example
<hno> Tsvetan, yes, but untested.
<Tsvetan> cool
<hno> Or, no, not the packer. But we do have the driver.
<Tsvetan> when we made the NAND images with Linux
<Tsvetan> everything packs fine
<hno> and Linux tools for packing.
<Tsvetan> but then there is no free space in the NAND
<Tsvetan> so you cant install anything new with apt-get
<Tsvetan> which makes this image useless
<Tsvetan> as to add something you have to generate new pack
<Tsvetan> for each new install you want to do
<hno> Tsvetan, how big did the rootfs get?
<Tsvetan> if we have Linux which can boot from NAND like from the SD-card we will start shiping with Linux on NAND
<Tsvetan> I dont remember
<Tsvetan> but the images are less 2G
<Tsvetan> so there is at least 2G free
<hno> images are compressed and mangled...
<Tsvetan> but when we flash the image with livesuit the NAND is always full after it
<Tsvetan> and no space for anything else to be add
<Tsvetan> we didnt dig too much anyway
<hno> wingrime, for example what?
<Tsvetan> in this direction
<hno> Tsvetan, ok.
<wingrime> hno: something intersting in bootloader drop
<Tsvetan> hno keep me in the loop if Linux on NAND is working we will immediately replace Android with Debian on the boards with NAND flash
<hno> wingrime, yes, many explanations to how the Allwinner bootloader is borked, and some more details on the A20 SDRAM controller.
<wingrime> hno: nice, also driver, are you about nfc driver?
<hno> the AW team working on the bootloader clearly needs a bit more time to test their changes.
<hno> wingrime, nfc? nand?
<hno> nfc is something else entirely..
<wingrime> hno: Nand Flash Controller
<hno> I have the AW GPL released A20 sources for the Nand driver for both u-boot and kernel.
<hno> think both have been pushed to my github.
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<hno> have not had time to look further into the nand controller, but at least the controller version in A10/A13 is relatively well understood now.
<hno> just lacking time to implement.
<wingrime> hno: it need also cache and ramdomization level to code
<wingrime> hno: but I prefer use kernel frameworks for it
<wingrime> sigh... ext4 need block device , not mtd
<wingrime> best will be use dd for it
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<arete74> /join #lima
<hno> /join #kernel
<hno> err...
<arokux1> what could NC stand for?
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<rm> New Conglomerate
<rm> (or Not Connected, in PCB charts and the like)
<arokux1> rm, and if NC_CLK?
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<wingrime> oliv3r: ping
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<Turl> arokux1: you'll have to look at the code
<Turl> arokux1: I've seen SATA labeled as NC wrt clocks
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<ssvb> libv: that's a preliminary draft, but I will try to clarify it
<ssvb> libv: to me it does not looks like a correct dri2, but we just need to convince the blob to behave the way we want in order to get non-broken buffer swaps
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<wingrime> mripard_: ping
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<leowt> anyone here familiar with the sunxi nand driver ?
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<wingrime> Turl: ping
<Turl> wingrime: pong
<wingrime> Turl: I can't set clock rate in mainline for ir
<wingrime> Turl: clk_set_rate return -22
<Turl> wingrime: on what clock?
<wingrime> Turl: APB0->IR0
<wingrime> it must be 3 MHz
<Turl> 22 is invalid value
<Turl> wingrime: the apb0 clock is just a gate isn't it?
<wingrime> yes
<Turl> wingrime: you need to set the rate on the other ir clock
<wingrime> but I need apb_ir0
<Turl> wingrime: yes but apb_ir0 doesn't need to change rate
<wingrime> Turl: why?
<wingrime> Turl: I need set apb_ir0 to 3Mhz like original driver do
<Turl> wingrime: I doubt original driver does that
<wingrime> Turl: do
<Turl> wingrime: see "[PATCH RFC 8/8] ARM: sun4i: mod0 clocks", I think you are looking for ir0 clock there
<wingrime> Turl: i debug on sun7i
<wingrime> Turl: mripard's branch
<Turl> ir changes on ir0, not apb
<wingrime> Turl: yes, I know, clocks = <&apb0_gates 6>;
<wingrime> Turl: i request this
<Turl> wingrime: you also need <&ir0>
<Turl> and set rate on <&ir0>
<Turl> but <&ir0> not merged for sun4/5i, not even implemented for sun7i yet
<wingrime> Turl: second driver on hold....
<Turl> wingrime: no need to hold
<Turl> wingrime: add hack that ioremap() register and change value as seen on
<Turl> then when <&ir0> is available it is trivial to fix that
<wingrime> Turl: please show now
<Turl> wingrime: something like
<wingrime> Turl: you say, I need map register , than , change value
<Turl> check register address with docs, might be different
<leowt> ive soldered a nand flash to an olinuxino a13
<leowt> what should i have in concideration?
<leowt> im getting a bunch of PHY_PageReadSpare : too much ecc err
<Turl> leowt: make sure you add the magic stuff for your nand on the drivers
<leowt> Turl: what kind of magic? =)
<wingrime> Turl: nice, but how with dt?
<Turl> leowt: I dunno, it's nand properties, there is a huge table on driver
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<Turl> wingrime: with dt you can do hack like this
<leowt> Turl: can you point me the file?
<Turl> wingrime:
<Turl> wingrime: then use that fake <&ir0>
<Turl> might need to ignore errors on clk_set_rate etc but it should let you write mostly complete code
<wingrime> Turl:so I need use clock = <&ir0> instead?
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<Turl> wingrime: clocks = <&apb_gates N>, <&ir0>;
<wingrime> Turl: can you explain than symmax
<Turl> wingrime: then of_clk_get(np, 0) == apb gate and of_clk_get(np, 1) == ir0
<Turl> wingrime: it is a list of clocks
<wingrime> why I need add apb_gates ?
<Turl> clocks = <&clock1>, <&clock2>, ..., <&clockN>;
<Turl> wingrime: apb is bus, need it to communicate with ir
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<wingrime> Turl: but I not need apb handle
<veprbl> Hi all! Any admins from wiki?
<veprbl> I get this: The text you wanted to save was blocked by the spam filter. This is probably caused by a link to a blacklisted external site.
<Turl> wingrime: no, you need handle to the gate
<Turl> veprbl: what's your wiki username?
<veprbl> veprbl
<Turl> veprbl: please try again now
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<veprbl> Turl, now it works. Thanks!
<Turl> wingrime: apb ir gate needs to be enabled so ir has access to apb bus
<wingrime> Turl: ok,
<wingrime> Turl: so I need do clk_prepare_enable for apb?
<Turl> wingrime: yes, for both apb gate and ir0
<woprr> Jul 31 14:31:23 <oliv3r>woprr: great, i see in the a20 manual that transport stream control and status registers are ... empty.
<wingrime> Turl: also with difference between of_clk_get and devm_clk_get?
<wingrime> *witch
<woprr> well, there should be a extra manual for the A20 or it's the same for A20 from the A10 TSC man
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<Turl> wingrime: of_* is dt functions
<Turl> wingrime: devm_* means it's managed and you don't need to clean up
<woprr> what makes me wonder, only one controller for 2 inputs even on A10? well, V.1.0...
<Turl> wingrime: you should use devm_* I think, I'm just too used to of_ because I work on clk driver :)
* woprr is still waiting for UK Royal Mail / Olimex parcel incoming, tommorow or friday...
<Turl> wingrime: mripard_ can possibly explain difference between devm_clk_get and of_clk_get better
<wingrime> woprr: I gilty you , becose rssian mail much slowpocke
<woprr> eheh
<wingrime> 2.5 mounth last time
<wingrime> air mail)
<woprr> UK Royal Mail (small packets) is ship mail, not air? then it'll take 14 days
<wingrime> Turl: also, there is no anything that can overwrite settings that done directly?
<Turl> wingrime: don't feel bad, my cb2 still in customs since 2 weeks :)
<wingrime> Turl: ))
<Turl> wingrime: you mean if anything else will overwrite your ir0 hack?
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<Turl> wingrime: nothing else should be touching that register
<wingrime> Turl: than init order does not care
<woprr> airmail
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<woprr> for consumers... checking business products...
<Turl> woprr: no tracking?
<Turl> wingrime: I don't fully understand your question
<woprr> nope
<wingrime> Turl: can I set rate before I init abp and ir
<wingrime> clocks
<Turl> wingrime: yes, you should set rate before prepare_enable both clocks
<Turl> wingrime: if you set rate after you output undefined clock rate, maybe too high
<wingrime> Turl: also, for you, please, when you will submit patches for clocks set ir0 clock name not like "ir0" better use ir0_clk
<wingrime> Turl: I can't use it for ir0 : ir@
<wingrime> whith such collision
<leowt> Turl: my nand already there "MT29F16G08MAA"
<Turl> wingrime: hm?
<Turl> leowt: I dunno then :p
<wingrime> Turl: dt require indifender unique
<Turl> wingrime: maybe you should name your node "ir0_hack" so it doesn't ever conflict
<wingrime> Turl: its more about when it will be pushed
<Turl> wingrime: well, you will probably see it in 3.12-rcN, so not nearby future
<wingrime> Turl: also, devm_clk_get require some string for second argument
<wingrime> looks like name string
<wingrime> Turl: have no idea witch name it requires
<Turl> wingrime: probably the node name, eg ir0
<Turl> wingrime: you can use of_clk_get(np, #) for now until mripard_ shows up I suppose
<wingrime> include/linux/clk.h:368:13: note: eexpected ‘struct device_node *’ but argument is of type ‘struct device *’
<wingrime> Turl: ok I have it
<wingrime> of_node
<Turl> np is dt node yep (node pointer)
<nove> jemk, wingrime, i commited trace viewer with register names and bit fields, unfortunately the canvas lib used is very fragile(segfaults)
<arokux> some strange thing. CCM base is 0x01C20000, PLL1_CFG_REG with offset 0x0000, but then later in the table:
<arokux> PLL1-Core(Default: 0x21005000)
<arokux> Offset: 0x00 Register Name: PLL1_CFG_REG
<arokux> why the base of PLL1 changed from 0x01C20000 to 0x21005000
<arokux> ?
<wingrime> Turl: stay online ... still need config mux for ir
<Turl> arokux: that's not the base, that's the default reg value
<Turl> wingrime: ok
<arokux> Turl, oh, that makes sense!
<arokux> Turl, obliged
<Turl> wingrime: for parent you'll need to run clk_set_parent(clk, parent)
<Turl> wingrime: I think you will need another clock in the list (the parent)
<Turl> arokux: :)
<arokux> wingrime, working on mainline?
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<wingrime> arokux: yes
<wingrime> Turl: in witch cases setup paret required?
<arokux> wingrime, which clock do you add? I'm adding pll6, pll62 and pll6M
<wingrime> arokux: I working on IR
<arokux> wingrime, ok
<Turl> arokux: I implemented all those already
<arokux> Turl, where are they?!
<Turl> arokux: lakml
<Turl> arokux: "[PATCH RFC 0/8] sunxi clk: PLL4/5/6 and module 0 support"
<Turl> wingrime: well, usually it is not needed because parent is already set on uboot or is default
<wingrime> clocks = <&apb0_gates 6>, <&ir0_clk>;
<Turl> wingrime: but it doesn't hurt either
<wingrime> Turl: I get error when I try get second clock
<Turl> wingrime: how are you getting it?
<wingrime> ir->clk = of_clk_get(dn, 1);
<Turl> wingrime: make sure you have "[PATCH RFC 1/8] clk: sunxi: fix initialization of basic clocks" on your tree
<Turl> wingrime: there was a regression with fixed rate clocks
<Turl> that patch fixes it
<wingrime> Turl: nope
<wingrime> Turl: only mripard patches
<Turl> wingrime: grab that one from list then
<wingrime> small, I apply it with hands
<arokux> Turl, where is your tree?
<arokux> linux tree, I mean
<mnemoc> :q!
<mnemoc> err
<Turl> mnemoc: error: not vi
<mnemoc> :)
<Turl> arokux: bitbucket
<arokux> Turl, hm.. from the data sheet I see, that PLL6 is a fixed clock with 1.2GHz
<arokux> Turl, but you have some factors for it..
<Turl> arokux: check user manual
<Turl> A10 p43
<Turl> A13 p61-62
<wingrime> Turl: same after parch
<arokux> Turl, yes, but how comes this info is different? :$
<arokux> Turl, NC - NAND clock?
<Turl> wingrime: check debugfs, do you see clock?
<Turl> wingrime: make sure compatible is "fixed-clock", I fail at example
<Turl> arokux: welcome to allwinner docs :p
<Turl> arokux: NC = not connected, do not connect or sth like that I think
<Turl> but its sata if you look at the code
<wingrime> clk_dump clk_summary orphans osc24M osc32k pll6
<wingrime> Turl: witch defenetly
<arokux> Turl, let me please ask some basic question. those PLLs are configurable clocks. and depending on the devices you connect to the SoC you configure PLLs to output some frequency. is that right?
<Turl> arokux: yes, kind of for the most part
<Turl> arokux: except the devices are inside the SoC :P
<arokux> Turl, :)
<arokux> Turl, what will happen with your patch?
<Turl> arokux: mali and sata feed off the same pll from what I recall, we had issues with that in the past
<Turl> arokux: I need to complete it a bit, mostly checking docs and writing dt bindings for A10S/A13
<Turl> and clean some stuff
<Turl> but I didn't get any major complain on the code so far so it should be ok for merging for the most part
<arokux> Turl, is there any tree which incorporates all *mostly* reviewed patches?
<arokux> because I cannot understand what my work flow should be. for the usb host I need pll62 clock, which depends on pll6
<Turl> arokux: mripard's tree, or sunxi-devel if you want even not fully cooked up stuff
<Turl> arokux: yes, depending on stuff that is still not settled can be problematic
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<Turl> arokux: I'd say you should get mripard_'s sunxi-next branch
<Turl> arokux: and apply my 8-patch series on top
<Turl> and develop usb on a sun4i system for the time being if possible
<Turl> once the clocks stuff settles it should be relatively easy to rebase the usb code
<arokux> Turl, I'm very slow anyway, this everything is new to me.
<arokux> Turl, hm, mripard_ 's -next branch also does not contain your patch. should I add your patch to it locally?
<wingrime> Turl: ir0_clk , that I added not in tree
<wingrime> clock tree
<Turl> arokux: all 8 of them
<Turl> wingrime: check compatible and make sure it is "fixed-clock"
<Turl> wingrime: "fixed-rate" is wrong
<wingrime> yes I will try again
<wingrime> Turl: nice
<wingrime> Turl: next step, mux IR0 pins correctly
<wingrime> Turl: I want see remote control IRQ print
<wingrime> Turl: first step for make it work
<Turl> :)
<wingrime> Turl: sunxi driver decoded NEC protocol by self and use private keycodes
<wingrime> Turl: if I implemet all corectly it will handle all protocols and use use kernel keycodes
<Turl> yep :)
<wingrime> I hope it must not take a long time
<wingrime> Turl: but I can't bring all functions
<wingrime> Turl: we have 2 - normal DMA capable IrDA transmitter/reciver
<arokux> do you guys actually have one tree locally and then multiple remote tracking branches?
<wingrime> arokux: git - DCVS
<arokux> wingrime, so the answer is YES? :)
<wingrime> arokux: we have personal trees)
<arokux> and branches in it tracking let say mripard's sunxi-next, Turls, sunxi-clk, etc.?
<wingrime> looks like so
<wingrime> arokux: git is DCVS
<arokux> wingrime, ok-ok, I knew that in theory, now the practice comes
<Turl> arokux: well, I have remote repositories added on my tree
<Turl> even if I don't have the branches checked out they're there just waiting for me to do so if I need so
<wingrime> arokux: I use cubie2 branch from mripard now, becose it have required patches for work
<arokux> I see
<wingrime> arokux: you can add remotes to git
<arokux> yep
<wingrime> arokux: and cherry-pick or merge
<wingrime> that you need
<arokux> I kind of heard of all these things, but only now i'll work with them
<Turl> arokux: great resource if you want to familiarize yourself a bit with git first
<wingrime> Turl: where I can see pin finctiond in lernel
<wingrime> ?
<arokux> Turl, yep, thanks
<Turl> wingrime: pinctrl driver
<Turl> wingrime: check how emac pin mux is done on sun4i/sun5i dt
<wingrime> Turl: "drive" 0 - input 1 - output?
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<wingrime> Turl: question how do it with dt
<wingrime> oh
<arokux> wingrime, where are you from?
<wingrime> arokux: russia
<xenoxaos> speaking of where you're from....random question....anyone from austin, tx?
* xenoxaos is moving and needs friends
<jelly-home> to help you move? :-)
<arokux> what lends in stage/sunxi-3.4? something that will soon come to sunxi-3.4?
<mnemoc> yes, after some cleanup
<mnemoc> then a tag, and a jump to the next 3.4.y
<mnemoc> and a new stage spawned
<ssvb> mnemoc: what would be the next 3.4.y?
<mnemoc> 3.4.55 iirc
<ssvb> ok
<mnemoc> unless there is something against that $y
<libv> ssvb: if i read your explanation correctly, you are using dri2 copyregion?
<ssvb> libv: yes
<libv> the way this one works from the mesa side is that the handler for this first calls the drivers' dri2flush handler, and then this mesa handler calls xcb_copyregion
<libv> dri2flush is where the render is sent off to the hw
<libv> and it takes a while for such a thing to return, and i believe that the lot is stalled then, but i am not sure
<ssvb> I tried to use ScheduleSwap, but it was just adding extra complexity for no good (with the mali binary driver)
<libv> ok
<Turl> wingrime: look at how it is done for emac
<ssvb> libv: but the mali drivers are just weird, too much voodoo magic is need to make them work
<libv> maybe that is the way to make this less serial
<libv> we can try to fix this massive slowdown when something is halfway working on my side
<ssvb> but how do you do it with the framebuffer?
<libv> i schedule a job, and then the fully threaded job handling runs through the motions and waits for the fragment shader to return, and flips when it does.
<libv> once i have sent off the job, i can continue building up frames
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<libv> the flip is tied to the return of the fragment shader job, and i do not have to wait in the main thread for it to return and then manually do the flip
<ssvb> but it does not seem to be very different from dri2
<ssvb> can you do DRI2SwapBuffers from this thread?
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<ssvb> even with the framebuffer, flip does not happen instantly after the ioctl call returns
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<libv> the latter is irrelevant, as long as i can continue to build up the next frame without being blocked on the kernel returning
<libv> dri2swapbuffers is something that is done for me.
<ssvb> it may be relevant if you don't want to start writing something to the old buffer which is still visible on screen
<libv> ssvb: this buffer address is fed in right before the fragment job is sent off to the kernel
<libv> the thing is, i can only send off the _vertex_ job to the kernel when i receive the flush
<wingrime> function: ir0, groups = [ PB3 PB4 ]
<libv> i am beating the mali framebuffer driver because i am able to schedule just as aggressively as it does
<wingrime> Turl: pinmux-functions show "current selected" function?
<oliv3r> wingrime: pong
<libv> with what i am using in mesa now, it's going to be a dog
<wingrime> Turl: or simply avl
<Turl> wingrime: did not understand your question
<Turl> what is avl?
<wingrime> avaliable
<ssvb> libv: in any case, the mali blob seems to be also threaded (DRI2GetBuffers and DRI2SwapBuffers may be called out of order relative to each other)
<oliv3r> wingrime: limited bandwith? :)
<Turl> wingrime: you mean the .h file?
<wingrime> oliv3r: linux-sunxi IR driver decode NEC protocl by own and use private keymap
<wingrime> Turl: no, I about debugfs entry
<libv> ssvb: there seems little way around that imho
<wingrime> Turl: how I can get current selected gpio function
<libv> somewhere between gettig the buffer location and layout, and telling the windowing system that the buffer is filled properly, some rendering needs to take place
<wingrime> using debugfs
<Turl> wingrime: I don't know, never used pinctrl debugfs
<ssvb> libv: what if you just request a bunch of buffers via DRI2GetBuffers beforehand and then do DRI2SwapBuffers as the results are ready?
<wingrime> Turl: I only added pins function to DT
<ssvb> libv: with many buffers you can really deeply pipeline it without any need to wait for anything
<wingrime> Turl: emac driver have no any interactions with gpio
<libv> let's see...
<Turl> wingrime: emac driver has pinctrl code, look for it
<Turl> or maybe it is on mdio part
<oliv3r> Tsvetan: yeah mtd driver should make live beautiful for default images ;)
<wingrime> Turl: witch line
<ssvb> libv: that's how r3p2 works, as shown at the bottom of
<wingrime> Turl: I can't find any "gpio" in sun4i-emac
<ssvb> libv: DRI2GetBuffers and DRI2SwapBuffers can be reordered relative to each other
<ssvb> libv: they don't really need to be interleaved this way
<libv> ssvb: that's all beside my point.
<wingrime> Turl: pin 36 (PB4): (MUX UNCLAIMED) (GPIO UNCLAIMED)
<libv> i do not have the ability to asynchronously tell mesa's glx code that my rendering is finished
<libv> i get told to flush, and that's it. i have to wait for it to be done
<ssvb> libv: is mesa so broken?
<libv> otherwise copy_region will happen before the fragment shader is done or has been started
<oliv3r> arokux: NC is 'secret rename' was probably SATA or something, the wiki 'fixed' the naming
<libv> ssvb: i would find that _very_ questionable
<libv> but this is what i have seen so far
<libv> mesa seems to be broken, or intel has some backdoor mechanism through fences and stuff, that i do not have access to
<ssvb> ok, I probably will not understand without looking at the mesa code
<arokux> oliv3r, wow.. i didn't know existed
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<ssvb> libv: how does mesa handle softpipe/llvmpipe? are they using dri2 for it or just something like xshmputimage?
<libv> i haven't looked yet
<libv> i cannot use gallium as that enforces full shader integration from the start
<libv> s/integration/assimilation/
<libv> with intel style driver i can plug in the binary compiler as needed
<wingrime> Turl: strange behavior, required part for pin config was in cubie2.dts
<libv> and cwabbott can then go and use the supposedly generic shader compiler infrastructure written for intel
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<oliv3r> wopr yeah TS manual you should take form a10 dir
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<Turl> wingrime: you will have to ask mripard_ about that, I haven't even seen that dts :)
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<arokux> oliv3r, I should pay more attention to wiki.
<wingrime> Turl: crap, still no any irq
<arokux> oliv3r, are you trying to put everything on the wiki? it can be much better than pdfs indeed.. there is a possibility to unite some sunXi
<wingrime> Turl: sunxi original driver show irq coming
<wingrime> Turl: but mine still not
<Turl> wingrime: did you configure irq?
<wingrime> Turl: yes
<wingrime> it shows as clamed
<Turl> make sure clock register is correct
<ssvb> libv: I think, I'm starting to understand what you want, sorry for being slow
<wingrime> void __iomem *reg = ioremap(0x01c20000+0x34,0x4);
<ssvb> libv: the mali style dri2 implementation is a dead end because it is doing stuff in a non-orthodox way (and I'm moving xf86-video-sunxifb in this "wrong" direction)
<ssvb> libv: it would be interesting to trace the real intel driver
<Turl> wingrime: I don't think it is 0x34
<oliv3r> wingrime: i'm almost done unifiying and cleaning it up
<oliv3r> wingrime: but yeah, sunxi-ir does NEC the hardway
<oliv3r> so doing a proper kernel driver == win
<wingrime> Turl: its from oringial driver
<Turl> wingrime: must be sun3i address
<Turl> wingrime: correct one is 0xb0
<ssvb> libv: I have an atom n450 here, maybe it makes sense to give it a try (if this hardware even has some opengl support)
<Turl> 1<<31 on, 0<<24 source 24M, 3<<16 for divisor
<Turl> wingrime: ^
<ssvb> libv: but other than the peformance of the buffers handling, is integration of lima into mesa going well?
<oliv3r> arokux: i tried initially; but with all these pdfs' it's a LOT of work, for little use
<oliv3r> arokux: but yeah, having it all wikified would be the best, just need someone doing the work ;)
<oliv3r> if you look at the 'memory map' you see what is documented so far
<arokux> oliv3r, allwinner should help! :D
<oliv3r> wiki for their manuals; absolutly :)
<oliv3r> not gonna happen ;)
<oliv3r> yeah i've backread
<oliv3r> and then silence :p
<libv> ssvb: the work you do for the binary driver is valid
<libv> as long as i do not have a mesa driver it is the only way
<wingrime> Turl: thanks
<wingrime> Turl: you saved tons of my time
<wingrime> Turl: I get IRs from IR
<wingrime> *IRQ
<libv> the work is advancing slowly, as this is the first "old style" mesa driver written from scratch
<libv> there is nothing that can by copy/pasted and then hacked
<libv> all that's out there is either completely crufty, or has grown organically
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<wingrime> Turl: main challenge begins now
<oliv3r> wingrime: it might be real easy ;)
<oliv3r> teh sun4i-ir driver is rather small
<oliv3r> and most of it is doing the NEC protocol
<libv> about not picking up on what i am trying to say, don't worry, you look at it from the other side of the mirror here
<wingrime> oliv3r: I still need undersand how RC framework works
<wingrime> oliv3r: also, LRADC much simpler, but I can't test it easy on cb
<libv> intel just flushed its command buffers on the dri2 flush command and then returns
<oliv3r> no buttons on CB i think
<oliv3r> wingrime: to bad Tsvetan didn't have any dev boards anymore
<Turl> wingrime: great :)
<libv> ssvb: in any case, it is not too important right now, first i need to show a triangle
<wingrime> Turl: I hope hackless way will be avaliable soon
<libv> ssvb: we can worry about this issue later
<arokux> Turl, what is your base you are adding patches to? mripard's sunxi-next?
<libv> when there is actual code to work with
<arokux> oliv3r, well, hyper-references are better then dumb pdfs
<libv> right now, i am trying to plug limare program linking into mesa
<oliv3r> and fixable :p
<Turl> arokux: torvalds' master
<arokux> Turl, hm.. but mripard has some additional code which is just about to lend in torvald's master.
<Turl> arokux: sure, but keeping external dependencies to a minimum helps
<Turl> and as I don't need any of that code, I just use torvalds' tree :)
<oliv3r> wingrime: i'll try to push sunxi-ir.c to ml tomorrow
<arokux> Turl, how do you know you are not using it in the first place? :)
<wingrime> oliv3r: nice
<wingrime> oliv3r: it 100% same ?
<oliv3r> 92%
<wingrime> oliv3r: whats differs
<ssvb> libv: ok, no problems, we can support the mali blob as good as we can for now
<Turl> arokux: because? :)
<oliv3r> wingrime: diff sun5i-ir.c sun4i-rc. -u; only 20 lines or so
<oliv3r> wingrime:
<ssvb> libv: it's just that there was this buffers size mismatch bug on window resize in r3p0 and I did not know a usable workaround for it
<wingrime> oliv3r: it means 100%
<wingrime> oliv3r: minor changes
<Turl> arokux: I'm working on clocks, so I don't need i2c or clocksource patches
<oliv3r> wingrime: yeah it's nearly identical
<arokux> Turl, I see. I mean who knows what the mripard is doing, but you seem to know it :)
<ssvb> libv: and there was some hope for maybe mali r3p2 upgrade, which kinda negatively affected the motivation trying to make something usable out of r3p0 :)
<wingrime> oliv3r: it more stange
<ssvb> libv: but now it looks like r3p0 can also make it
<wingrime> oliv3r: uart IP can work in IrDA mode
<wingrime> oliv3r: so IR mostly useless
<oliv3r> uart IP? what makes you say that?
<oliv3r> i wouldn't be supprised if it's somehow related
<oliv3r> irda and uart are very much alike
<wingrime> 19.4.9. UART Modem Control Register
<wingrime> 1: IrDA SIR Mode enabled
<Turl> arokux: well, if we didn't know what each one of us is doing it'd be pretty confusing and messed up :p
<wingrime> oliv3r: witch means IR mostly useless
<Turl> oliv3r: sid! :p
<wingrime> oliv3r: as can be on gpio
<Turl> wingrime: IR can do CIR maybe?
<wingrime> oliv3r: yes , i think
<wingrime> MIR and CIR
<arokux> Turl, then send you patches to linux-sunxi ML too :P
<oliv3r> Turl: wingrime wanted sunxi-ir unification done first!
<oliv3r> i think CIR is most usefull
<Turl> oliv3r: my laptop has a winbond cir thingy I never got running on linux :(
<oliv3r> iirc cir is 'RC" no?
<Turl> C is for customer iirc
<Turl> err, consumer
<oliv3r> exactly, RC sounds consumerish
<oliv3r> see, mostly used for RC
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<oliv3r> time for bed :) nn all
<wingrime> Turl: nice , one press , one irq, but after 4rd I get endless irq, witch means FIFO overflow
<Turl> wingrime: :) need to clear fifo
<wingrime> CIR MIR and FIR
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