<Guest70096>
we have develop a hardware already, which is follow 96 board standard, CPU is A64, we just need a compatible operation system, such as ubuntu or android
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<bamvor>
Guest70096: Which country are you stay?
<bamvor>
There are difference contact in different region/country.
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<cnxsoft>
Guest70096: Several other companies have already ported OS to Allwinner A64 including Pine64 and Banana Pi, so you may have to adapt those. Allwinner has certainly provided you with an Android SDK for A64.
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<Guest70096>
we are in china
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<wens>
willmore: yup
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<bamvor>
Guest70096: For business, you could also connect the guys in offcial account of wechat (search "96boards"). That guys focus on the business in China
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<Guest70096>
thanks bamvor, but how to connect the guys in offcial account? :)
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<tuxillo>
hi
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<bamvor>
Guest70096: Search "96boards" in official account(公众号)
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<ErwinH>
montjoie: stmmac works on OrangePi PC2 as well.
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<ErwinH>
Haven't done iperf3 yet.
<montjoie>
thanks for the test
<ErwinH>
Quick iperf3 test to an BpiM1 gives 816/423
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<montjoie>
anybody with a running bpim2+ ?
<montjoie>
ErwinH: 423 is with -R ?
<ErwinH>
Yup
<montjoie>
strange, normally TX < RX
<ErwinH>
emac driver gives more or less similar results. 841/555
<montjoie>
probably the loss on RX is due to CRC offload disabled
<ErwinH>
I guess the server isn't the best.
<ErwinH>
But haven't got anything better at the moment.
<ErwinH>
Since normally it should reach 950/950 with the emac driver.
<KotCzarny>
it depends greatly what is on the other side too
<ErwinH>
I know, but I haven't got a decent server running at home.
<KotCzarny>
having good laptop/switch is enough
<ErwinH>
Let's use my macbook pro... O wait, it doesn't have ethernet...
<KotCzarny>
:>
<KotCzarny>
seriously? no headphone jack either? ;)
<KotCzarny>
and which part of the pro is having less features?
<ErwinH>
It's just old enough to have a headphone jack :)
<KotCzarny>
s/less/fewer/
<KotCzarny>
thinkpads usually had good intel ethernets
<beeble>
the thunderbolt adapter is not bad in terms of performance
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<KotCzarny>
yup, thunderbolt bus isnt bad
<KotCzarny>
but.. dongles
<KotCzarny>
i hate things hanging from mobile devices
<ErwinH>
The wifi connection of the MBP is really good, so this works fine.
<beeble>
99% of the time i only use wifi
<ErwinH>
3 cables hanging from the side while it's at my desk is enough :)
<KotCzarny>
seems like half of allwinner chip comes from designware/stmicro ;)
<MoeIcenowy>
A working out-of-tree driver for mainline kernels is at [2].
<jelle>
KotCzarny: haha
<KotCzarny>
jelle: it should be in wifi category
<jelle>
oh there is a link I'm just blind
<KotCzarny>
similar to 'boards with ethernet' etc
<jelle>
MoeIcenowy: thanks
<MoeIcenowy>
maybe it's just Allwinner bought wafers from ST then packaged
<montjoie>
raaaah I forgot a ++ and now my bpim2+ is stuck scanning phy, and no remote power off:(
<KotCzarny>
montjoie: at least you can go back to real boards ;)
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<montjoie>
but i want to know the end of this PHY mistery
<KotCzarny>
:)
<KotCzarny>
forced cliffhanger for now
<montjoie>
where do come this ac200 phy
<rellla>
has simplefb->hdmi for H3 already landed in mainline uboot/kernel or do i have to take jernej's u-boot-tree for now?
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<MoeIcenowy>
rellla: still need jernej's tree.
<MoeIcenowy>
montjoie: could you at first sort out your sun8i-stmmac driver? ;-)
<MoeIcenowy>
at least send a RFC first ;-)
<rellla>
MoeIcenowy: it's because i don't get X started with moinejf's DE2/hdmi patches. maybe because simplefb also tries to load as i can see in dmesg...
<MoeIcenowy>
rellla: could you share your dmesg?
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<MoeIcenowy>
Is there anyone WIP on SPI support of U-Boot?
<montjoie>
MoeIcenowy: you can find it on github, and I wanted to test gigabit on H3
<MoeIcenowy>
but at least you're sure it can work, right?
<MoeIcenowy>
or I will ask my friend if he wants to help you
<montjoie>
MoeIcenowy: yes more dedicated since dma register are different
<montjoie>
but the code size is not large
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<MoeIcenowy>
I think after moinejf abondoned sun8i-de2-drm, I may continue it
<MoeIcenowy>
as I have V3s -- a SoC with DE2, but without HDMI
<MoeIcenowy>
rellla: megous's branch do not have simplefb enabled
<MoeIcenowy>
so you're only meeting issues with sun8i-de2-drm
<MoeIcenowy>
try to enlarge your CMA pool?
<MoeIcenowy>
(I mean the main CMA pool, not the VE one
<rellla>
MoeIcenowy: as i use the build environment of armbian, i saw, that they patch uboot with simplefb patch. so i had both enabled, because i use a custom kernel config.
<MoeIcenowy>
sun8i-de2-drm now do not have coexist with simplefb
<MoeIcenowy>
but if the kernel do not have simplefb patch, U-Boot will just fail to add simplefb address
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<rellla>
i will try to enlarge CMA pool as this may be a reason, why my system does not boot, if i set ve_reserved memory to 100MB+
<MoeIcenowy>
I mean the main CMA pool, not the VE one
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<MoeIcenowy>
CONFIG_CMA_SIZE_MBYTES option
<rellla>
yes, i too. but doesn't take ve it's mem out of that pool?
<MoeIcenowy>
seems that currently ve uses a dedicated pool
<MoeIcenowy>
and then the main pool is allocated
<MoeIcenowy>
the ve pool should be lowest 128M
<MoeIcenowy>
but main pool is usually at the top of system dram available
<rellla>
i will do some investigations ;)
<MoeIcenowy>
[ 0.000000] Reserved memory: created DMA memory pool at 0x000000004a000000, size 96 MiB [ 0.000000] OF: reserved mem: initialized node cma, compatible id shared-dma-pool
<MoeIcenowy>
here's my A33 device
<rellla>
[ 0.000000] Reserved memory: created DMA memory pool at 0x43d00000, size 80 MiB
<noblock>
One question; I tried the linux kernel 4.9.4 from megous on an opipc board; After loading the 'de2' modules, I've the following error: sun8i-de2 1000000.de-controller: failed to allocate buffer with size 8294400
<rellla>
^^ mine. this is for ve
<rellla>
[ 0.000000] cma: Reserved 16 MiB at 0x7e800000
<rellla>
^^ and this is cma? seems to be quite small.
<noblock>
Likely a kernel configuration issue (CONFIG_CMA_SIZE_MBYTES was set 8); Do you know how to fix this issue?
<rellla>
MoeIcenowy: thanks for the hints. have to go now...
<MoeIcenowy>
rellla: if your screen is 1920x1080, I can promise 16MiB is far from enough for main pool ;-)
<noblock>
MoeIcenowy: Do you have the optimal value?
<MoeIcenowy>
noblock: I choose 64MiB
<MoeIcenowy>
but I do not have large screens...
<MoeIcenowy>
my largest screen is 1024x600
<rellla>
MoeIcenowy: yeah, yesterday i plugged in my tv. and that is FullHD :p
<MoeIcenowy>
I only used the TV to try the Composite output of my C.H.I.P. ...
<MoeIcenowy>
and now I even do not use TV in such a way -- as I bought a Composite to USB dongole
<MoeIcenowy>
dongle *
<MoeIcenowy>
montjoie: one of my friend in Sinovoip says that it's RTL8211D/E
<montjoie>
just in case , other RGMII ?
<MoeIcenowy>
I think so ;-)
<MoeIcenowy>
but why do you got an AC200 id...
<montjoie>
the furthermore strange thing, is that I am nearly sure to get good perf when working on sun8i-emac on that board
<MoeIcenowy>
but bad perf from sun8i-stmmac?
<montjoie>
I got the same perf with sun8i-emac now
<montjoie>
good perf was in the past in my memory
<MoeIcenowy>
maybe your memory needs some fsck
<montjoie>
just thinked that I have a loghost for all log, and in august the board has a RTL8211E Gigabit Ethernet
<MoeIcenowy>
the schematic also says a RTL8211D/E
<MoeIcenowy>
can sun8i-emac recognize it as RTK phy?
<montjoie>
its the phylib that does that
<MoeIcenowy>
but it may also be IP block bug
<MoeIcenowy>
montjoie: seems that it's impossible to be an AC200...
<MoeIcenowy>
H3 do not even have a RSB
<montjoie>
if it give me random id, what a chance to alsways have the same
<KotCzarny>
h3 doesnt have rsb?
<MoeIcenowy>
the vendor of AC200 is just the same of H3
<MoeIcenowy>
so it may be the default value
<MoeIcenowy>
KotCzarny: yes
<montjoie>
lol, according to loghost it seems that yesterday I booted with sun8i-emac and realtek phy was here
<montjoie>
I am mad
<KotCzarny>
:>
<KotCzarny>
we are all mad here
<MoeIcenowy>
only mad people can stay at #linux-sunxi ;-)
<KotCzarny>
and ib irc ;)
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<montjoie>
I think to see the problem, with sun8i-emac the phy slot is 0
<montjoie>
with stmmac, in DT I set 1
<MoeIcenowy>
;-)
<montjoie>
so two phy wired
<MoeIcenowy>
maybe 1 is the internal phy?
<montjoie>
and 0 is the dhcp for phy, so it seems realtek answer first
<montjoie>
but if you probe 1, it become the default
<montjoie>
and so it is why my "probes just after" give me ac200 for slot 0
<MoeIcenowy>
how can a network port have two phys?
<MoeIcenowy>
we know, a H3 cannot even communicate with an AC200
<montjoie>
EMAC speak on the MDIO bus
<montjoie>
multiple phy can be on that bus
<MoeIcenowy>
but you have only a single port, right?
<montjoie>
yes
<MoeIcenowy>
so how can this single LAN port be wired to two PHYs?
<montjoie>
physically it can, if only one is powered
<montjoie>
seems weird
<MoeIcenowy>
what's the PHY ID of H3 EPHY?
<montjoie>
need to print it
<montjoie>
the phy_print_status do not print it
<MoeIcenowy>
can the ID be retrieved by some userspace tool?
<montjoie>
but another problem, I wrongly said that I use reg 1 with stmmac
<montjoie>
I use 0 also
<montjoie>
the Id can be printed via phydev->id
<MoeIcenowy>
what the hell...
<montjoie>
just need to boot my opipc
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<KotCzarny>
tkaiser, ircing from customer address space?
<montjoie>
MoeIcenowy: but certainly the ac200 is the internal phy
<montjoie>
and something in my driver still select internal phy
<MoeIcenowy>
montjoie: I think you should try to probe the phy id of both internal and external phy with sun8i-emac...
<MoeIcenowy>
I suspect stmmac have problem while probing phy
<MoeIcenowy>
according to bpi m2+ schematics the EPHY pins are NC
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<montjoie>
by EPHY you means internalphy ?
<MoeIcenowy>
yes
<MoeIcenowy>
the part is named as EPHY in datasheet and on every schematics
<MoeIcenowy>
is there anyone working on the SPI support of mainline u-boot for sunxi?
<MoeIcenowy>
(full SPI support, capable of using SPI NOR in u-boot main binary
<Wizzup>
MoeIcenowy: we (where I work) might in the very near future, but have no previous driver dev experience
<MoeIcenowy>
I have also no u-boot driver experience
<montjoie>
MoeIcenowy: I think the problem is that stmmac register the mdio before any int/extphy choose, and so libphy probe internal phy and get stuck on it
<montjoie>
mdio_reset should fix that
<dgp>
MoeIcenowy: my u-boot fork has a crappy driver that works enough for the sf command to work
<MoeIcenowy>
dgp: thanks
<MoeIcenowy>
has a base to modify from is a good thing ;-)
<dgp>
It's very crappy (expects the SPL register and clock setup to have been done) but it's good enough to boot the opiz from SPI
<MoeIcenowy>
I'm also thinking a good way for SPI clock and pinctrl initialize
<MoeIcenowy>
and this patch do not easily apply on current master...
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<IgorPec>
it looks like he is already gone ...
<MoeIcenowy>
erwinh is him?
<MoeIcenowy>
mripard: I have heard the Lichee Pi Zero board will have two versions of on-board storage, both SPI, but one will be SPI NOR, the other will be SPI NAND
<MoeIcenowy>
how should this be dealed with in device tree?
<MoeIcenowy>
have two device trees?
<IgorPec>
MoeIcenowy: no, i don't know his nick here.
<IgorPec>
if any
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<MoeIcenowy>
IgorPec: so how should I contact him on fourm.armbian.com?
<IgorPec>
use private message or send him email. i think it's written in profile
<IgorPec>
martinayotte@gmail.com
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<nik123>
I have an chinese branded Allwinner A20 tablet, tried to find it on the wiki. No results. The tablet is pretty much bricked, android doesn't even try to boot just a blank screen. I wonder if theres a way to run Linux on this, because it has USB OTG and a HDMI port. Any help would be appretiated :)
<MoeIcenowy>
without a booting Android it's very difficult to extract info to run Linux on it
<nik123>
Recovery mode still works though...
<nik123>
Should that help?
<nik123>
And also a board number
<MoeIcenowy>
if you can get a shell under recovery mode ;-)
<nik123>
adb?
<MoeIcenowy>
I think stock android recovery's adb is nearly unusable
<MoeIcenowy>
only enough for sideload :-(
<nik123>
well you're right, I have to tell you that
<MoeIcenowy>
do you have serial access?
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<nik123>
I have UART, but no UART to USB though...
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<nik123>
This tablet is screwed: exec '/system/bin/sh' failed: No such file or directory (2)
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<nik123>
Sorry I have unstable internet access...
<nik123>
The MSI_Primo73 ROM almost worked but I think some "legit hardware check" validation protocol, prevented it from booting. In the recovery mode touch screen and the buttons worked flawlessly. Not to mention adb
<nik123>
Can I try using that version of UBoot
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<MoeIcenowy>
maybe you'd try it
<nik123>
But I just noticed that this tablet doesn't have a Vol + key. Instead it uses the back button as the FEL key. Atleast I think...
<nik123>
What settings are for the serial, trying out something...
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<MoeIcenowy>
dgp: trying your driver
<MoeIcenowy>
"dm tree" can see a spi device, but it do not probe
<nik123>
the flash was overwritten many times, I don't know if I'll get anything useful but ok
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<tkaiser>
beeble: Off-topic: Apple's Ethernet Thunderbolt adapter is not even using TB but PCIe instead ;)
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<MoeIcenowy>
dgp: oh seems the subnode of SPI NOR flash scared the uclass ;-)
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<IgorPec>
MoeIcenowy: he is comming :)
<willmore>
MoeIcenowy, WRT the NAND flash chips, it looks like a separate DT node should be used as that kind of chip will require a different driver--it's more like parallel NAND flash where blocks have ECC and need that taken care of in software.
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<willmore>
In other words, you can't just read the memory out like NOR flash, you have to read a block+ECC and do the ECC calculations on it.
<willmore>
Winbond has some chips out, but I can't find any mention of them on aliexpress, so I can't order any to play with.
<Wizzup>
there's lots of them on ebay and aliexpress
<beeble>
willmore: never used it in a product. only onfi nand
<willmore>
beeble, thanks.
<willmore>
MoeIcenowy, looks functionally similar to the winbond chip--at least for reading a few pages of the datasheets.
<willmore>
Plenty of details that differe--especially when writing or using special features like OTP or UID features.
<willmore>
But, that's for userspace anyway.
<beeble>
and with onfi nand you would read the data raw too. if the nand controller supports the ecc algorithm (and length) it can be offloaded
<beeble>
if not it's done in software
<willmore>
One limit would be the need to implement the 4 byte address read instruction for accessing memory >16MiB. But, if we can use continuous read, that's not a limitation.
<willmore>
beeble, yep, and the controller on the SoC will do most of that for you. Such assitance isn't built into SPI ports. :)
<montjoie>
it is the return of great realtek phy:)
<MoeIcenowy>
and I believe the Allwinner BROM cannot deal with SPI NAND well
<MoeIcenowy>
montjoie: congrats ;-)
<montjoie>
still bad perf
<MoeIcenowy>
Orz
<montjoie>
I note "change syscon / reset the board then register MDIO bus"
<montjoie>
interesting that the internal phy branded as 100 could negociate 1G
<willmore>
MoeIcenowy, if it just does continuous read, then it's okay. It looks like the read data+ECC instructions are different. The "just read data" are the same.
<beeble>
but why would you want to use spi nand anyway? that would be like having the worst of both worlds
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<MoeIcenowy>
yes I agree
<MoeIcenowy>
but it's the most easy way to integrate high-capacity storage onto V3s boards
<MoeIcenowy>
V3s do not boot from SDC2
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<MoeIcenowy>
(The V3s datasheet advertises it that support SPI NAND
<MoeIcenowy>
(but I really doubt it
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<nekomona>
BROM Failed or workable with bugs everywhere?
<beeble>
MoeIcenowy: boot from spi nand would be no issue. all it does is reading boot0/spl. default behaviour is to have internal ecc active on reads
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<beeble>
so you would get your bootloader exactly as you would with a spi nor flash
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<martinayotte>
MoeIcenowy: did you got chance to look at the patch ?
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<MoeIcenowy>
martinayotte: yes
<MoeIcenowy>
I also refreshed into 4.10-rc
<martinayotte>
Good ! Feel free to try with "Water Level" too if you feel that would be better
<martinayotte>
As I've answered yo your email, it is a derivative of the existing patch of sun4i-spi.c, but using RXFUL/TXEMP instead of 3/4F 3/4E
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<martinayotte>
Oh ! revizing it, I discover that a comment is left un-edited : /* Transmit FIFO 3/4 empty */ should be /* Transmit FIFO empty */
<martinayotte>
:-)
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<MoeIcenowy>
oh I checked the datasheet
<MoeIcenowy>
there's no 3/4 things in spl-sun6i
<MoeIcenowy>
at least on H3 and V3s
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<martinayotte>
Yes, that is the reason why I've decide to use FULL/EMPTY, at least until I understand the "Water Level", but since it seems to work fine, no emergency for WL
<MoeIcenowy>
you mean {T,R}X_TRIG_LEVEL in reg 0x18?
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<MoeIcenowy>
martinayotte: If I send out this patch, can I just add Signed-Off-By: you?
<martinayotte>
Yes, TRIG_LEVEL, I didn't studied yet how it is working ...
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<martinayotte>
Signed-Off-By ? sure ! or it can be both of us too ...
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<MoeIcenowy>
oh I suddenly understand why empty+full can also work reliably when reading the commit message of spi-sun4i
<MoeIcenowy>
the spi controller will pause transmission when empty/full
<MoeIcenowy>
s/\/full//g
<martinayotte>
For TRIG_LEVEL, it seems that both are 8 bits, so maybe it simple as writing the level desired
<MoeIcenowy>
but how to decide the level is a problem ;-)
<martinayotte>
Could be simply 3/4 of 64 bytes, so RX_TRIG=48 and TX_TRIG=16
<martinayotte>
64 bytes for H3, but some other sun6i are 128 bytes
<MoeIcenowy>
but I now more prefer to work on the DE2 ;-)
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<martinayotte>
Of course, since with 100% Full/Empty seems to work, at least for me, I have other things too : making André's FIT work on my H5 ;-)
<martinayotte>
apritzel : I've seen you submit this morning ! Congrats !
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<mripard>
MoeIcenowy: I don't know, you might want to ask bbrezill1, but if it can't be autodetected, yes.
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<wens>
montjoie: fyi, the rtl8211e responds to both 0 and the phy address programmed through the phyaddr pins
<wens>
montjoie: 0 is kind of like a broadcast address
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<montjoie>
wens: yes, but I believed that the probem would be a priority problem
<montjoie>
in fact I needed to chaneg syscon and reset before probing MDIO
<montjoie>
like I just said before, it is interesting that the internal phy accept RGMII and negociate gigabit link
<montjoie>
so even opipc could in theory gain some perf beyond 100Mbit/s
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<ssvb>
MoeIcenowy: there is no such thing as SPI pause
<ssvb>
if the FIFO buffer overflows or underflows, then the data is lost
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<ssvb>
a higher level protocol can implement data checksums and re-transmission
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<ssvb>
the only reliable way to implement support for SPI messages larger than the FIFO size is to use DMA
<willmore>
ssvb, If the master runs out of data to TX, then to can just stop clocking out data. If it runs ou of RX buffer, it can just stop the clock, no?
<ssvb>
willmore: hmm, you are right
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<willmore>
So, since this is a master interface. We can pause. Slaves are boned, though.
<ssvb>
we need to check this with an oscilloscope though
<willmore>
That's why the high speed modes in these chips have extra delays for the high speed modes.
<willmore>
Yes, good idea. Always verify.
<willmore>
I think my scope speaks SPI.
<willmore>
I need up get one of my Opi1 back up and running so I can test on it.
* willmore
has been working with 3d printers recently and had to set all of his SBCs aside.
<willmore>
ssvb, my 128Mb SPI chips still aren't here. :(
<ssvb>
it should be also possible to easily add artificial pauses and check whether everything is alright
<willmore>
And to do clock speed testing.
<willmore>
Datasheet for H3/5 says 100MHz. Sure....
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<ssvb>
willmore: when you are using jumper wires to connect the SPI chip, the actual speed limit is much lower than this
<ssvb>
flashrom guides recommend using the shortest possible jumper wires
<ssvb>
"Running SPI at only 6 MHz might be not fast enough and adding something like ~0.5 second to the boot time (needed to transfer ~500KB of the main U-Boot binary). In order to improve boot time a little bit, probably the SPL header can be extended to include a special optional field for the maximum supported SPI clock speed and also the number of dummy cycles for the Read Data Bytes at Higher Speed (0Bh) command. This information
<ssvb>
can be added to the SPL header by the firmware flasher software"
<beeble>
i could look if i have some boards left as a giveaway if you are improving the spi driver :)
<beeble>
just would have to replace the nor. it only has 32mbit at the moment
<ssvb>
the flasher can perform a "speed grading" procedure by checking various SPI clock speeds
<willmore>
beeble, taht would be martinayotte who's doing that. I'm not at that point.
<willmore>
ssvb, I was almost thinking of making a little bootstrap loader that's customized to the board/chip.
<willmore>
But, maybe we can paramaterize the chip performance well enough to have a generic bit of code.
<willmore>
I'm not that far into the Feyman problem solving yet.
<willmore>
beeble, I have some 128Mb chips in the same package coming.
<willmore>
And I am going to try to get some NAND chips too.
<beeble>
my boards don't hav soics. had to stick with wson area and height
<ssvb>
the SPI code in the SPL can just read the clock speed limit info and the dual-spi capability bit from the header, this way it can remain extremely small
<willmore>
I need to also look into the flash layer on linux and see if it supports SPI as a physical layer.
<beeble>
on linux you can use it with mtd and ftl as a blockdevice
<willmore>
ssvb, I don't have enough knowledge of all the SPI chips to know how uniform they are. Looks like the low speed read is the same on the few I've looked at. The higher speed transfers *seem* the same, but I'm not as confident of that.
<willmore>
beeble, cool, thanks.
<willmore>
Because the NAND SPI chips have ECC for sectors.