#linux-sunxi on 2017-06-20 — irc logs at freenode.irclog.whitequark.org

2015-02-18 19:37 Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi

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11:02 <paulk-gagarine> mripard_, hey, I'm looking to setup a nanopi neo2 -- I've seen on the list that you already accepted patches for those and merged them, but I cannot find them on https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git/

11:02 <paulk-gagarine> mripard_, should I look some other place?

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11:06 <plaes> paulk-gagarine: wens has sunxi-next branch in github

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11:15 <Net147> plaes: how's the CCU patchset going?

11:17 <plaes> Net147: sata is still b0rked

11:17 <plaes> and haven't had time to look at it for a month now..

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11:19 <plaes> SATA has fixed post divider

11:20 <paulk-gagarine> plaes, neat, will look into that

11:22 <Net147> plaes: yeah, I still need to wrap my head around how the clock hierarchy works...

11:22 <mripard_> paulk-gagarine: we changed of git repo, s/mripard/sunxi/

11:22 <paulk-gagarine> mripard_, oh, good to know :)

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11:26 <Net147> plaes: the SATA clock registers are being set incorrectly? or not set at all?

11:26 <plaes> Net147: I couldn't figure out how to plug in the post-divider

11:27 <plaes> SATA clock has multiple parents

11:27 <plaes> HDMI patchset included some improvements for multi-parent support

11:27 <mripard_> plaes: what's wrong with CCU_FEATURE_FIXED_POSTDIV ?

11:28 <plaes> IIRC it was unimplemented

11:29 <plaes> SATA is div clock

11:30 <mripard_> what do you mean ?

11:30 <codekipper> Hi, does anybody know if there is a nighly build for uboot images?

11:30 <mripard_> is it a post-divider or a divider ?

11:32 <codekipper> just thinking about putting together some instructions for booting arch linux and if there is uboot images out there then no building is required

11:33 <jelle> instructions for arch are simple :-)

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11:34 <codekipper> yeah I know....thought it maybe useful for others...nightlies seem broken here http://dl.linux-sunxi.org/nightly/u-boot-sunxi/u-boot-sunxi-mainline/u-boot-sunxi-mainline-latest/

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12:06 <Net147> mripard_: I guess he is trying to work out how to model a clock based on the formula "parent * N * K / M / 6" or "parent * N * K / (M * 6)"

12:08 <vinz0r> what can be done to help mainlining pinebook support?

12:09 <jelle> vinz0r: first off, working on the wiki? http://linux-sunxi.org/Pine_Pinebook

12:11 <Net147> plaes: how about using SUNXI_CCU_DIV_TABLE for pll_periph_sata_clk?

12:12 <vinz0r> jelle, ok I can look into that

12:15 <Net147> plaes: just have the .div values multiplied by 6

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12:19 <mripard_> Net147: why not N * K / M, with a post-divider of 6

12:19 <mripard_> instead of hacking things around

12:23 <Net147> mripard_: fixed_post_div is implemented by NK clock, not NKM clock?

12:23 <mripard_> then implement it in NKM clocks

12:27 <mripard_> plaes: which SATA clock are we talking about, the PLL-SATA or the SATA one?

12:28 <wens> if it's the PLL-SATA one, you have to have a common base clock for both PLL-SATA and PLL-PERIPH

12:32 <Net147> wens: sata clock is then "base clock / M / 6" or alternatively "base clock / (M * 6)"?

12:36 <wens> pll6-base = 24*N*M, pll-sata = pll6-base / M / 6, pll-periph = pll6-base / 2

12:36 <wens> Net147: does it matter if you multiply first or not?

12:37 <Net147> n / M / 6 is mathemtically the same as n / (M * 6)...

12:38 <Net147> A20 manual has (...) / M / 6, R40 manual has (...) / (M * 6)

12:38 <wens> so you mean in the clock implementation?

12:41 <Net147> not sure, I have almost no experience with clocks...

12:42 <Net147> so the question would be how to model "pll6-base / M / 6" using ccu_div

12:43 <mripard_> M, with a post-div

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12:45 <Net147> so implement new ccu_m clock type?

12:47 <Net147> oh it's in ccu_div

12:48 <Net147> so I guess implement fixed post-divider support in ccu_div then

12:48 <plaes> sry, back from meeting..

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12:50 <Net147> I guess https://github.com/plaes/linux/commit/43fe15c41a4896bf196fee4788840032f8e1188b is supposed to do that

12:51 <plaes> Net147: yeah, I couldn't get it working

12:52 <plaes> but it was before mripard_ improved the multi-parent clock support

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13:04 <Net147> mripard_: are you able to spot any issues there?

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13:06 <mripard_> no, but I'm not sure what the issue is

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13:10 <Net147> plaes: perhaps there is nothing enabling and setting the SATA clock rate in the DT? A20 manual says clock output should be equal to 100 MHz if the SATA is on

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13:16 <Net147> plaes: something like https://github.com/Icenowy/linux/commit/dfd373bfe564b4b234c4c0f06da8bff65d09dab1 and https://github.com/Icenowy/linux/commit/f6bdd48ac2a6040cde26b10fefbd0029f8ed04ee

13:19 <plaes> Net147: where do you see the rate ^^

13:25 <Net147> plaes: the default values for N, K, M fir PLL6-SATA configure a 100 MHz SATA clock by default which is the rate required for SATA...

13:27 <mripard_> plaes: the DT will probably not help you with it

13:27 <mripard_> but what is your issue exactly with this clock ?

13:28 <plaes> I couldn't get it working unless, I had already enabled it in u-boot

13:28 <plaes> but it's been a month I last played with it

13:29 <mripard_> yeah, but it doesn't work isn't really a description, it's a statement

13:30 <plaes> like I said, I don't remember currently

13:30 <mripard_> is clk_set_rate failing? Some other function ?

13:30 <Net147> plaes: PLL6 is disabled by default, it needs to be enabled for the SATA clock. perhaps nothing enables PLL6 if SATA is disabled in U-Boot.

13:30 <mripard_> is it failing because of what, you try to set a rate and it doesn't returns the proper rate, something else?

13:31 <mripard_> if the rate returned in the clock frmaework ( that you can check through debugfs) is the right one, is it consistent with the value in the register?

13:31 <mripard_> etc...

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13:35 <Net147> I can check the PLL6-SATA register using "devmem2 0x01c20028" for example

13:35 <Net147> mripard_: do you use devmem2 for that purpose as well?

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14:17 <mripard_> yes

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15:36 <nove> discussion of fuchsia and gpl -> https://news.ycombinator.com/item?id=14583566

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19:33 <plaes> mripard_, Net147: hah.. it was more stupid ...

19:34 <plaes> I didn't have SATA clock in the clocks :(

19:34 <plaes> only CLK_AHB_SATA

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23:24 <MoeIcenowy> mripard: will patches sent now be only applicable on 4.14?

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