<MoeIcenowy>
wens: so how should we do ugly hacks on H3 r_ccu?
<wens>
no idea atm :(
<MoeIcenowy>
yes a strange problem
<MoeIcenowy>
but megous reported that it blocked the implementation of proper DVFS on boards with SY8106A
<wens>
a work around for now might be to just keep r_i2c enabled from the bootloader
<wens>
MoeIcenowy: only the ar100 clk is unaccessible? or all the clks? or all the prcm registers?
<MoeIcenowy>
wens: only the clk
<MoeIcenowy>
the PRCM gate and reset registers are OK
<wens>
argh :/
<MoeIcenowy>
so we didn't found any issues before
<MoeIcenowy>
as the R_PIO doesn't need the accurate frequency of CLK_APB0_PIO
<MoeIcenowy>
but I2C needs accurate bus clock frequency to derivate the I2C clock
<MoeIcenowy>
oh the "APB0_CLK_DIV_REG" is also not accessible
<MoeIcenowy>
but "APB0_GATING_REG" and "APB0_MODULE_RST_REG" are accessible
<MoeIcenowy>
CIR mod clock is also accessible
<MoeIcenowy>
maybe we should make apb0 a fake clock on H3?
<wens>
sounds like there might be some guard bits for the core clocks, like in the CCU
<willmore>
MoeIcenowy, how inaccurate is the clock that I2C can't use?
<wens>
undocumented perhaps
<MoeIcenowy>
wens: nope, in secure the clocks work well
<MoeIcenowy>
in non-secure they don't work
<MoeIcenowy>
I tried to start the kernel in secure, and the clocks are okay
<wens>
MoeIcenowy: non-secure guard bits :)
<willmore>
That's an akward way of asking, sorry. I2C doesn't need a very accurate clock--10% off should name no difference.
<MoeIcenowy>
willmore: the real clock is 24MHz, and the wrong value is 32kHz
<MoeIcenowy>
do you think it can work? ;-)
<willmore>
Nope. :)
<willmore>
Well, actually it will work, but it's slow as hell.
<willmore>
Might make DVFS a little impractical.
<MoeIcenowy>
nope it doesn't
<willmore>
The whole Dynamic part of that won't be very dynamic
<MoeIcenowy>
you will get a 24MHz I2C bus
<wens>
lol
<MoeIcenowy>
do you think any I2C slaves can work under 24MHz?
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<willmore>
Yeah, both 32KHz and 24MHz are a bit far form 400KHz.
<wens>
willmore: the kernel readout of the clock is wrong, not the actual rate
<willmore>
wens, ahh, okay.
<MoeIcenowy>
yes, so the kernel thought the clock is 32KHz, so the divider is not set
<MoeIcenowy>
but it's really 24MHz
<MoeIcenowy>
so the I2C bus become 24MHz
<willmore>
Yeah, that won't work. If it were 32KHz instead, it would work.
<willmore>
I'm bitbanged I2C from an old PC and I'm pretty sure the 'clock rate' was all over the damn place.
<willmore>
I2C is meant to be used by chips without any timing sources, so it's very forgiving.
<MoeIcenowy>
wens: I think a temporary hack will be to use bit-banged I2C to control SY8106A
* willmore
drops out of the conversation.
<MoeIcenowy>
but the whole clock tree is then wrong
<MoeIcenowy>
I think it's possible that other peripherals may fail
<MoeIcenowy>
e.g. r_uart
<MoeIcenowy>
r_uart also has an internal divider which is connected to bus clock
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<wens>
MoeIcenowy: maybe do the override from u-boot? as in replace the i2c compatible and add the gpio lines
<MoeIcenowy>
if someone uses r_uart it will also fail...
<MoeIcenowy>
wens: I think override this from U-Boot is a uglier hack
<MoeIcenowy>
In fact in our old clock dt the apb0 clock is fixed 24M from osc24M
<MoeIcenowy>
maybe we should do the same thing in H3 CCU driver
<wens>
why should we do so for the H3 CCU driver?
<wens>
the H3 CCU driver clearly works, and we already properly configure the non-secure access bits in it
<MoeIcenowy>
nothing
<MoeIcenowy>
H3 CCU driver doesn't care it
<MoeIcenowy>
the main secure/non-secure switches just don't work
<MoeIcenowy>
oh they're defaultly set to 0x7, which allows all pll operations
<MoeIcenowy>
yes set it back to 0x0 prevented proper boot from non-secure
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<MoeIcenowy>
so we have a broken, but sometimes works secure/non-secure division...
<MoeIcenowy>
strange
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<MoeIcenowy>
wens: the secure controlling register of r_ccu is 0x01f015d0
<MoeIcenowy>
and the bit 1 is controlling ar100 clk
<MoeIcenowy>
and apb0 divider
<MoeIcenowy>
and this register can be written in non-secure world
<MoeIcenowy>
not a good design, but for us it will be more easier to solve the problem!
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<MoeIcenowy>
oh it's set in ATF -- at plat/sun50iw1p1/sunxi_security.c
<MoeIcenowy>
wens: I suggest we fix this in U-Boot, but however this will make people with not-up-to-date U-Boot cannot have correct clock...
<wens>
that is unfortunate, but u-boot is the proper place for it, as it is u-boot that puts the system in non-secure mode
<wens>
MoeIcenowy: please send a fix for u-boot, maybe with ondrej as the issue reporter
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<MoeIcenowy>
wens: U-Boot fix sent
<MoeIcenowy>
but without reported-by tag
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<chrisf__>
maz: That was painful but I finally have an SGI from Core 0 (at EL2) causing an exception on Core 1 (also at EL2). HCR_EL2.IMO did need to be set for this to happen. I think the ARM docs (god I hate them) are ambiguous. 0->Phys IRQ while executing at exception levels LOWER than EL2 are not taken at EL2. 1->Phys IRQ while executing at EL2 OR LOWER are taken in EL2.
<maz>
chrisf__: out of curiosity, what are you trying to do SGI-ing at EL2?
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<chrisf__>
maz: I'm writing a very small code footprint system to use the chip as a math processor for another system communicating over SPI. I needed to be able to start cores, signal between them and react to SPI interrupts. The choice of EL2 wasn't significant it's just what the ATF started my code in.
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<chrisf__>
I've never worked at this level on anything more complicated than an M4 before.
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<maz>
chrisf__: sounds like a fun project! :-)
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<chrisf__>
maz: Making progress but I had no idea how complicated these chips were ... another part of the project uses a C51 - that's a bit easier!!!
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<maz>
chrisf__: it is an acquired taste. I've spent too much time on this shit to remember the simple stuff... ;-)
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<FergusL>
Anyone tested the "matrix" code from FriendlyArm? compiling it on Armbian Nanopi M1 Plus right now and it worked great! I spent some time looking at the various WiringPi and other solutions but this one doesn't look too bad, it even has SPI and I2C!
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<FergusL>
erh, no, no luck, I tried the RTC program but it fails because /dev/ has not the same structure
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<kilobyte>
with dwmac-sun8i I get plenty of fatal send/write errors with nbd, -emac worked ok
<kilobyte>
other uses of network seem to work ok, so do certain uses of nbd (like badblocks -w)
<kilobyte>
[ 251.938384] block nbd0: Send data failed (result -11)
<kilobyte>
[ 251.961022] print_req_error: I/O error, dev nbd0, sector 2206344
<kilobyte>
[ 251.955676] block nbd0: Attempted send on invalid socket
<kilobyte>
[ 251.950034] block nbd0: Receive control failed (result -32)