<Hauke>
haev to fix some problems in the kenrel tomorrow
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<smaeul>
is there a list of syscon registers anywhere beyond https://linux-sunxi.org/SRAM_Controller_Register_Guide ? I'm looking at the H5 BROM, it's reading from 0x01c000a4, and I can't find any description of what that's supposed to be
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<montjoie>
smaeul: have you tried the datasheet/usermanual ?
<smaeul>
yeah, the data sheet only has two registers (VER_REG and one for the emac) for syscon
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<smaeul>
montjoie: in my very much WIP dissection of the H5 BROM at http://dpaste.com/196Z1VK, the mysterious code is func_2de8, which turns bits 0 & 1 of the undocumented register on and off in a loop. it's called several different times with different parameters. I assume it's some sort of debugging feature, meant to be detectable from outside the CPU
<smaeul>
similar to func_2e84, which is also called several times with a monotonically increasing parameter, and writes to addresses off in the middle of nowhere
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<smaeul>
At 0x3098 in the H5 BROM, Allwinner provides a handy little function for writing eFUSEs! Fortunately, it's not called from anywhere
<smaeul>
I guess that means their toolchain doesn't discard unused functions
<smaeul>
I still haven't found any code for handling secure boot -- the only function that reads the LCJS fuse immediately throws away the bottom 16 bits
<smaeul>
is there a separate BROM for secure boot mode or something?
<MoeIcenowy>
smaeul: maybe you need to dump another copy of BROM with a board that burns the eFUSE bit?
<MoeIcenowy>
I think it's said so
<MoeIcenowy>
yes the H5 detailed datasheet said it in memory mapping
<MoeIcenowy>
N-BROM is at 0x0~0x7FFF
<MoeIcenowy>
S-BROM is at 0x0~0xFFFF
<smaeul>
so _that's_ what that means
<smaeul>
in non-secure mode, I just got two copies of the N-BROM
<MoeIcenowy>
I think so
<MoeIcenowy>
and in secure mode you can get S-BROM
<smaeul>
I only have one board atm, so I don't think I'll be doing that soon, but thanks for the confirmation
<MoeIcenowy>
if apritzel is here maybe he can grab a copy of S-BROM on A64
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<smaeul>
I got what I really wanted to know out of the BROM -- info about suspend/wakeup and cpu 1-3 initialization
<MoeIcenowy>
as he did the brave experiment on a Pine64
<smaeul>
and then after that, since I'm really ambitious, I want to try to get suspend working
<MoeIcenowy>
oh good job.... very thanks
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<adfad666>
Wiki says no cpufreq support for H3, any specific reason it's not supported?
<MoeIcenowy>
adfad666: no one is mainlineing it ;-)
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<adfad666>
so it's just a lack of resources issue not any technical issue
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<lvrp16>
correct me if i am wrong, cpufreq would require integrating the 100 different ways people control voltage on the boards?
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<dwelch>
where can I find information on bringing up the other cores on an H5? Getting them out of reset or whatever state they are in at the end of u-boot?
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<MoeIcenowy>
ATF
<MoeIcenowy>
Call PSCI
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<dwelch>
interested in register accesses not calling a function or a command line operation. where are the pcsi registers defined?
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<dwelch>
are the clocks enabled and resets released to the core, but it is now in the arm core that releases the rest?
<dwelch>
C_RST_CTRL implies these cores have not been released, this is chip vendor specific not in the ARM core. releasing those resets does not start those cores running so far as i can tell
<dwelch>
so trying to understand the steps that preceed or follow releasing reset.
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