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<wens>
hitech95: likely because people didn't have hardware to test other word lengths
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<hitech95>
anarsoul, I just cheched on all usermanuals of A1X/A20/A31/A33/A83 and looks like that at least all socs can have 24 bit data. Only the A83 is capable of 32bit word.
<KotCzarny>
yay for high quality output to spdif! ?
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<hitech95>
KotCzarny, I'm looking at the code of i2s/codec. to find out why it don't fully work on A33/R16. Yesterday I discovered that the soc i2s interface is limited at 16bits...
<KotCzarny>
maybe there were some silicon bugs
<KotCzarny>
or they've dropped the support out of laziness
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<hitech95>
KotCzarny, it may be but looks strange to me that from a10 to a80 the same problem has not been fixed! (i'll check on BSPs)
<KotCzarny>
they reuse silicon blocks
<KotCzarny>
sometimes they add something new, but luckily for us, before H6 everything was very similar to previous releases
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<hitech95>
yup but i think that if a block don't work they will fix it....
<KotCzarny>
dreamer
<KotCzarny>
ask montjoie about CE status and bugs :>
<hitech95>
what is ce?
<KotCzarny>
crypto engine
<montjoie>
benching distcc for compiling kernel with allwinner boards... not bad (18min with cubieboard2+R40+OpiPC)
<hitech95>
oh, is that bugged? on hardware side?
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<KotCzarny>
since he is here i will let him comment and vent (maybe)
<montjoie>
sometime got bug, sometime algo got retired from datasheet
<hitech95>
on openwrt we discussed about a possible idea to hw implement cypto engine as FPGAs so via a blob manuf. could implement and fix the algo. That would be really cool!
<hitech95>
Is the only one I have. First experience with Allwinner :)
<KotCzarny>
grab some cheap orange pi h3 board
<KotCzarny>
they are quite nice
<KotCzarny>
also make great hacking boards
<KotCzarny>
unkillable, small, cheap
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<hitech95>
Right now I have more or les 5 rpis around my house. And a couple more inside a drawer. No idea what to do with them.
<KotCzarny>
h3 soc is quite popular
<KotCzarny>
and very well mainlined
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<hitech95>
yup I have seen. A friend have a Npi neo 2 or similar. he uses is as a small NAS with OMV.
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<hitech95>
I'm working on R16/A33 because i'm doing my own hardware in case neutis module don't comes out. (my original plan was to use the GR8 socbut NTC closed) :(
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<escalion>
hitech95: nice clean patch :)
<escalion>
hitech95: also with the rPi's cluster them!!
* escalion
hates rPi's though
<hitech95>
escalion, thx, it is a WIP i'm still adding stuff that is just a git diff piped into a file for reference.
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<hitech95>
escalion, I also hate rpis. are overrated
* escalion
agrees
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* micken
hates DWC
* micken
hates closed hw
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* hitech95
wandering why allwinner don't add a detailed clock diagram for their hardware.
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<wens>
uh, someone wrote me and said pine 64 lts is r18, and doesn't have support in the kernel
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<micken>
anyone
<micken>
On Pinebook , it looks like USB0 is OTG and not EHCI
<wens>
it's dual routed. in host mode it should be routed to ehci/ohci
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<libv_>
oh wow, nextthingco really did go bankrupt
<libv_>
heh.
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<micken>
wens: ah ok I see it now
<micken>
also which uart is connected to the serial debug?
<micken>
there is a address register for otg-echi-ohci.. I wonder if ehci is first in that space
<micken>
all will probably be reveild when I boot up a existing os :)
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<micken>
running software allways tells the truth
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<hitech95>
does someone know ehy a codes should have steh sys clock connected to two differet AIF? Why and when I should switch between them?
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<hitech95>
god dammit, my stupid keyboad: does someone know why codecs should have the sys clock connected to two differet AIF MCLKs? Why and when I should switch between them?
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<MoeIcenowy>
wens: I'm recently using Pine A64-LTS to debug
<MoeIcenowy>
it can just use SoPine w/ Baseboard image
<hitech95>
MoeIcenowy, I don't have a pine 64, but what is the difference of the 64 LTS to the standard one? Was that a hardware fail?
<MoeIcenowy>
the DRAM chip changed
<MoeIcenowy>
from DDR3 to LPDDR3
<MoeIcenowy>
due to price ;-)
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<hitech95>
LDDR3 is chaper?
<KotCzarny>
someone wrote recently that lpddr3 != ddr3l
<KotCzarny>
or something
<MoeIcenowy>
currently, it is
<MoeIcenowy>
KotCzarny: of course LPDDR3 != DDR3L
<MoeIcenowy>
DDR3L is a kind of DDR3 that can run at a slightly lower voltage.
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<hitech95>
ddr3l is the "more or less standard" dd3. Initial ddr3 was running at more than 1.35V. so ddr3l are chips that runlower than ddr3 voltage of 1.5V. and have nothing to do with LPDDR3.
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<MoeIcenowy>
Pine A64-LTS also migrated from A64 to R18
<MoeIcenowy>
(although the same die
<MoeIcenowy>
due to R18 will be sold for longer than A64
<hitech95>
ah ok. I was just asking that! If I remember correctly the only difference id a bit on the OTP about bsp version or something
<hitech95>
Like android versions/linux. not so sure about that. I have read something similar somewhere
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<wens>
hitech95: like if the SoC is sleeping, the I2S MCLK will be off, but if you want the codec to keep working, you could have SYSCLK be clocked from some other AIF, like the one connected to BB or BT
<wens>
hitech95: think audio under low power conditions
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<hitech95>
wens, ok but on I still don't get it. MCLK on R16 is not mentioned anywhere if not on the codec. The codec SYSCLK can be from AIF1 and AIF2. AIF1 and AIF2 clock can be from MCLK or PLL. BSP force the PLL on each request. To mee looks like that AIF1 and AIF2 closk are equals.
<wens>
MCLK is the signal name in I2S
<wens>
hitech95: again, you have to think of it as a standalone codec, but with AIF1 directly connected to an I2S controller inside the SoC, instead of externally
<wens>
that I2S controller can output MCLK to the codec
<wens>
(I suppose)
<wens>
btw AIF1 and AIF2 clocks refers to clocks that drive the interface
<wens>
so the setting in question means, which clock do you want to use as a reference clock for each interface
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<wens>
ugh.... scratch that
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<wens>
hitech95: AIF1CLK and AIF2CLK refer to clocks that drive the AIFs
<wens>
so yeah, if you stop AIF1 and AIF2 is not working either, the codec stops
<wens>
and to use MCLK, you have to first enable MCLK in the I2S controller side
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<wens>
but mostly I think the DAPM widgets and routing for clocks in the sun8i-codec driver need to be reworked
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<hitech95>
wens, i'm "rewriting" the whole driver right now. I'mt ring to understand what is missing and how to add. Right now that clock stuff is working but make no sense on how in configured. I'm not an expert.
<hitech95>
tha ac100 driver is too huge, is like 10k of lines O.o
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<hitech95>
wens, my work so far: I shoud have added all the important DPAM, i need to add the digital volume control for AIF1/2. I also miss the mux inside the first digital block (MONO REVERSE AVG). I'll try to implement sysclk/hw_parms calls to better manage clocks dividers in base of the dai_id so each dai could be indipendent from the other. AIF3 is not implemented and I have no idea on how I could do it ('m still a noob). For reference: