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<
wens >
paulk-leonov: do you remember where you got the address for sram C on H3 from? there's really nothing at that address AFAICT.
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<
paulk-leonov >
wens: IIRC it wasn't from the docs but from trying by playing with the bits to map to CPU or not
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<
jernej >
apritzel: could we somehow push forward them for next release?
17:53
<
jernej >
Updating H6 related DT files would also help, mostly to fix ethernet mac on some boards and so I can finally add TV box with DDR3 config
17:53
<
jernej >
apritzel: when is most appropriate time to send such patches?
17:55
<
apritzel >
jernej: you can send patches anytime
17:55
<
apritzel >
jernej: if there are clear fixes in there, we can try to merge them straight away
17:55
<
jernej >
btw, patch I just send, maybe it could be regarded as fix and be included in next stable?
17:56
<
jernej >
but on the other hand, there is no H6 board config with DDR3 yet
17:56
<
apritzel >
jernej: yeah, I saw, I need to have a look at it's regression potential
17:57
<
jernej >
yeah, for sure
17:57
<
apritzel >
if that affects H6 DDR3 boards, that basically means 0, I guess ;-)
17:58
<
jernej >
exactly, so now I want to add one such board (Tanix TX6 TV box)
17:58
<
jernej >
but that's material for another cycle
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<
jernej >
patch actually touches all boards - it changes common code
18:00
<
jernej >
It's present in LibreELEC nighty images for months and no issue regarding that was reported...
18:00
<
apritzel >
jernej: that's great!
18:01
<
apritzel >
jernej: and I can then probably revive my Eachlink H6 Mini box support as well
18:02
<
jernej >
apritzel: does it make sense to send DT update patches now? by the time they will be merged, they will probably be old..
18:03
<
apritzel >
jernej: yeah, that's probably one of the very few good reasons to
*not* send patches now
18:04
<
apritzel >
jernej: you could send the 5.11-rc1 versions then, that should fall in the U-Boot merge window
18:05
<
jernej >
ok, I hope I won't forget
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<
apritzel >
jernej: I dimly remember this
18:18
<
apritzel >
jernej: does it fix something? I am not sure this wasn't a red herring?
18:18
<
jernej >
apritzel: As patch says, DRAM size is misdetected...
18:20
<
jernej >
I ocassionally noticed such issue
18:22
<
jernej >
but barrier shouldn't have effect at this point, unless BROM enables cache or something
18:22
<
apritzel >
yeah, barriers are tricky, so I need to have a look into the ARM ARM first
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<
apritzel >
writel has already a dmb barrier, and my gut feeling tells me that dsb doesn't give us everything we would want in this case (since it doesn't guarantee completion)
18:27
<
apritzel >
for pushing it into the device (DRAM here), we would need to read it back
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