05:50 <GitHub192> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/vJGWF

05:50 <GitHub192> artiq/master d3753c9 Sebastien Bourdeauducq: runtime: get IP and MAC from flash storage

05:50 <GitHub192> artiq/master 4d31194 Sebastien Bourdeauducq: runtime: load idle kernel from flash storage

06:03 <GitHub135> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vJG43

06:03 <GitHub135> artiq/master 1684586 Sebastien Bourdeauducq: test: add unittest for core device watchdog

06:08 <GitHub176> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/vJGBO

06:08 <GitHub176> migen/master 01e2343 Sebastien Bourdeauducq: doc: remove cordic

10:52 <GitHub20> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vJZrs

10:52 <GitHub20> artiq/master 62669f9 Sebastien Bourdeauducq: soc: factor timer, kernel CPU and mailbox

13:42 <GitHub35> [migen] enjoy-digital pushed 2 new commits to master: http://git.io/vJnVz

13:42 <GitHub35> migen/master 70bc4ec Florent Kermarrec: mibuild/platforms/pipistrello: add _n suffix to usb fifo pins

13:42 <GitHub35> migen/master aea7308 Florent Kermarrec: mibuild/platforms/minispartan6: rename ftdi_fifo to usb_fifo and fix rd_n/wr_n swap

13:46 <travis-ci> m-labs/migen#25 (master - 70bc4ec : Florent Kermarrec): The build passed.

13:46 <travis-ci> Build details : http://travis-ci.org/m-labs/migen/builds/60834381

13:54 <GitHub174> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/vJn6E

13:54 <GitHub174> misoc/master 8aa3fb3 Florent Kermarrec: com/uart: add tx and rx fifos....

14:18 <GitHub170> [misoc] enjoy-digital pushed 3 new commits to master: http://git.io/vJn9b

14:18 <GitHub170> misoc/master 23ba1cc Florent Kermarrec: targets/minispartan6: add USBSoC (working, should also be usable on pipistrello)

14:18 <GitHub170> misoc/master da0fe2e Florent Kermarrec: liteusb: refactor software (use python instead of libftdicom in C) and provide simple example....

14:18 <GitHub170> misoc/master 603b4cd Florent Kermarrec: liteusb: continue refactoring (virtual UART and DMA working on minispartan6)...

14:32 <sb0> _florent_, did you test the uart with artiq?

14:35 <_florent_> hi sb0, no sorry, I've tested it with the bios, flterm and liteusb (it uses it for the virtual uart over USB)

14:36 <_florent_> (I can do a test for ARTIQ but I have to set it up, if someone can do a quick test I'll really appreciate it :)

14:36 <sb0> please test it with artiq. I'm doing a lot of bug hunting already ...

14:40 <_florent_> OK I'll try to do in this weekend

14:40 <sb0> and well, I guess you'll need an artiq install at some point anyway to test the new cache system

14:42 <_florent_> yes I know this is not an excuse, I'll take the time to install it

14:44 <sb0> thanks :)

15:44 <GitHub49> [misoc] enjoy-digital pushed 2 new commits to master: http://git.io/vJcaI

15:44 <GitHub49> misoc/master 2312641 Florent Kermarrec: litescope: use full name in io.py

15:44 <GitHub49> misoc/master 1281a46 Florent Kermarrec: litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data)....

18:38 <GitHub77> [misoc] enjoy-digital pushed 4 new commits to master: http://git.io/vJCAS

18:38 <GitHub77> misoc/master cd3a51a Florent Kermarrec: litescope: fix missing source ack on LiteScopeWishboneBridge

18:38 <GitHub77> misoc/master a8b8af2 Florent Kermarrec: liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)

18:38 <GitHub77> misoc/master c03c41e Florent Kermarrec: litescope: rename host directory to software (to be coherent with others cores)

23:31 <cr1901_modern> sb0: http://urchin.earth.li/~twic/Sequenced_Packets_Over_Ordinary_TCP.html Unfortunately, I'm not sure how to implement this... yet!