00:10 <mindrunner> i have a couple of questions regarding verilator. I am able to simulate my design. I figured out that it loads the Misoc BIOS. How can I make it loading my own software as well? Also, I would assume that I can monitor Signals and so on while simulation. How can I do that?

01:22 <rjo> mindrunner: use flterm on the simulated serial port. or add a rom with the code.

01:49 <GitHub32> [misoc] enjoy-digital pushed 2 new commits to master: http://git.io/vJ9ho

01:49 <GitHub32> misoc/master 6908ddb Florent Kermarrec: litesata: cleanup README/doc

01:49 <GitHub32> misoc/master 5516a49 Florent Kermarrec: litesata: add doc for frontend

10:03 <GitHub17> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vJQaZ

10:03 <GitHub17> artiq/master a91bb48 Sebastien Bourdeauducq: gateware: adapt to misoc changes

11:21 <ysionneau> artiq repo reached 1000 commits o/

11:48 <larsc> and that apparently killed github

11:50 <ysionneau> =)