sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub50> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vT20C
<GitHub50> artiq/master 6c35d06 Sebastien Bourdeauducq: runtime: add missing include
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<travis-ci> m-labs/artiq#145 (master - 6c35d06 : Sebastien Bourdeauducq): The build is still failing.
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<sb0> origin of today's cool bug: http://pastebin.com/jEnjrz0q
<ysionneau> o_o
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<ysionneau> asyncio does not seem very production grade yet
<GitHub68> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/6c35d066fc65...785623be26fa
<GitHub68> artiq/master a670b9f Sebastien Bourdeauducq: tools/asyncio_wait_or_cancel: wait for cancellation
<GitHub68> artiq/master 785623b Sebastien Bourdeauducq: test/worker: adapt to new scheduler API
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<travis-ci> m-labs/artiq#146 (master - 785623b : Sebastien Bourdeauducq): The build was fixed.
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<ysionneau> travis is back in the game o/
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<GitHub48> [artiq] fallen pushed 1 new commit to master: http://git.io/vTwic
<GitHub48> artiq/master 1e393f5 Yann Sionneau: setup.py: add missing comma
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<travis-ci> m-labs/artiq#147 (master - 1e393f5 : Yann Sionneau): The build passed.
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<GitHub68> [artiq] fallen created upstream_master (+1 new commit): http://git.io/vTrLI
<GitHub68> artiq/upstream_master c91cd0a Yann Sionneau: pxi6733: use a writeable and c_contiguous numpy ndarray
<ysionneau> oops
<GitHub8> [artiq] fallen merged upstream_master into master: http://git.io/vTrLa
* ysionneau deleted the branch, wrong manipulation
<GitHub21> [artiq] fallen deleted upstream_master at c91cd0a: http://git.io/vTrLw
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<travis-ci> m-labs/artiq#149 (master - c91cd0a : Yann Sionneau): The build passed.
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<cr1901_modern> ysionneau: How does the LM32 MMU handle a context switch? Does it just fully flush the TLB?
<ysionneau> It depends
<ysionneau> You can enable tlb tag support
<ysionneau> then you just have to change the tag id when doing the context switch
<ysionneau> if you don't activate the tags in the tlb, indeed you need to flush the tlb
<ysionneau> tags are not fully implemented btw
<ysionneau> https://github.com/m-labs/lm32/blob/master/rtl/lm32_dtlb.v#L220 they are implemented in the DTLB
<ysionneau> but not in the ITLB yet
<ysionneau> but it should be almost a copy paste ...
<ysionneau> it's fully implemented in this qemu branch however : https://github.com/fallen/qemu/
<ysionneau> (tag support)
<cr1901_modern> How much extra hardware does it take to activate tags? Is it comparable to the ASID approach that ARM uses?
<ysionneau> it's exactly ASID
<ysionneau> I mean it's an address space ID, but I don't know if it works exactly like in ARM cores
<ysionneau> but yes that's the idea
<ysionneau> each tlb line has an ASID (or tag), and the line only matches if the ASID is the same as "current context ASID"
<cr1901_modern> See, I thought "ASID" was an ARM technology, not a generic concept (though I can see why it would be applicable generally)
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