01:05 <whitequark> rjo: good

03:17 <sb0> rjo, cr1901_modern so no scrolling in scan widget?

06:32 <cr1901_modern> sb0: I'll add it in today or tomorrow (prob the latter b/c prior engagements today)

08:06 <sb0> rjo, how good is semi-rigid coax for clock distribution?

08:06 <sb0> might be an acceptable intermediate solution that avoids the complicated, proprietary and RTM clock backplane

08:07 <sb0> and the output lines of the DACs will be cables anyway, which are also susceptible to the same jitter, so I wonder how much sense the clock backplane actually makes

08:09 <sb0> no RTM and FMC = more standard DAC/RF boards (can be mounted on a KC705 etc.), smaller rack, all connections always on one side

08:09 <sb0> but: no clock backplane, less space for components on the cards, potentially more digital noise

08:12 <sb0> oh there are even fully-rigid coax cables. never seen those...

08:13 <sb0> ah, it's for the high-power stuff it seems

08:19 <sb0> there's also the FPGA+DAC on the same board solution ...

08:19 <sb0> which should solve the space problem

10:34 <rjo> sb0: no scrolling?

10:35 <rjo> other than the two exisiting wheel modes (shift for npoints and ctrl for zoom)?

10:36 <rjo> sb0: we should avoid the rtm and the rtm backplane at almost all cost.

10:37 <rjo> sb0: semirigid is excellent but tedious and painful. rigid is perfect but even more painful and tedious.

10:39 <rjo> i would really love fmcs for stuff. even if we fail to do the nice approach of having the dac/adc on the base board and the analog circuitry on fmcs.

12:09 <GitHub99> [artiq] jordens pushed 2 new commits to master: https://git.io/vanVU

12:09 <GitHub99> artiq/master 5e7eff6 Robert Jordens: scanwidget: changes as of edaba53

12:09 <GitHub99> artiq/master 5714ffe Robert Jordens: scanwidget: draw based on font metrics (closes #328)

12:10 <rjo> sb0: could you try that pixel clipping again?

12:11 <GitHub90> [misoc] enjoy-digital pushed 1 new commit to master: https://git.io/vanVq

12:11 <GitHub90> misoc/master df3a45b Florent Kermarrec: intersonnect/stream: simplify Converter (now only works on raw bits) and add StrideConverter to handle first-level user fields

12:11 <cr1901_modern> rjo: Sorry I didn't notice #328. Thank you fo fixing it

12:47 <GitHub80> [misoc] enjoy-digital pushed 1 new commit to master: https://git.io/vanrm

12:47 <GitHub80> misoc/master cde39f3 Florent Kermarrec: interconnect/stream: add insert_chunks parameter to Converter (to be validated with ARTIQ's Analyzer)

12:50 <GitHub19> [misoc] enjoy-digital force-pushed master from cde39f3 to f962ed2: https://git.io/LjONPA

12:50 <GitHub19> misoc/master f962ed2 Florent Kermarrec: interconnect/stream: add insert_chunks parameter to Converter (to be validated with ARTIQ's Analyzer)

14:33 <sb0> cslwifi is wonderful. simply downloading their aware app without installing it, which you can do from a PC, unblocks free wifi access.

14:33 <sb0> *adware

14:36 <sb0> rjo, looks good now

14:40 <sb0> rjo, yes, with drag-and-drop like pyqtgraph does, when the zoom is too large to allow both cursors to be displayed

14:40 <sb0> actually, you could scroll anytime, but it is most useful in this case

14:58 <rjo> sb0: do you mean dragging the axis to move it? yes that's coming.

14:58 <cr1901_modern> rjo: I'll implement that tomorrow most likely

14:58 <rjo> ack.

14:58 <cr1901_modern> today if I have the time, but prior engagement

15:14 <sb0> rjo, yes

15:14 <sb0> rjo, so you'd send analog signals through the FMC connector?!

15:17 <rjo> sb0: yes.

15:20 <rjo> sb0: there are well matched and smooth differential transmission lines.

15:21 <rjo> doing it that way works very well for the usrp hardware. also with other digital signals on that connector.

15:21 <rjo> s/there are/these are/