sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
rjo, interesting that Joe managed to install the pipistrello package. obviously he still has the dev channel, as I removed the pipistrello package from main ...
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<sb0>
whitequark, despite your claim that mech pumps do not care what oil you use, I do get better vacuum after replacing the chinese gunk with the oil I brought
<sb0>
the pump is quieter, too
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<rjo>
sb0: ack. he also did python setup.py install
<mithro>
rjo: I also started digging into ISE to figure out how to disable the "rng" inside it - Didn't get all that far though. We get the same behaviour where with the exact same input, ISE generates both working and non-working firmware.
<rjo>
mithro: -R is the same as PYTHONHASHSEED=0
<rjo>
mithro: all i can hope to achieve here is consistency. if it fails consistently that's progress.
<mithro>
rjo: Ah, even with PYTHONHASHSEED=0 we are still getting the same failing behaviour with ISE
<rjo>
mithro: even the bitstreams that fail timing work pretty well. i have not seen a problem. and in another project we have been massively overclocking e.g. the multipliers and yet to observe problematic behavior (we would likely notice).
<mithro>
rjo: I had the faint hope that -R was being given to one of the ISE tools to make it use a deterministic random seed or something :(
<mithro>
rjo: It looks like the "Starting Placer Cost Table" might be in some ways related to a random seed
<sb0>
rjo, what's -R?
<mithro>
sb0: I just had that conversation with rjo :P
<sb0>
oh, sorry
<rjo>
mithro: that didn't change anything for me.
<mithro>
sb0: Ha, it felt like dejyavu :)
<mithro>
rjo: Oh well, it was what I found when randomly searching the interwebs for thoughts
<mithro>
rjo: I've been poking the Debian Reproducible guys about tips / hints on making ISE deterministic
<mithro>
rjo: they have a module which makes all time deterministic
<rjo>
but there are so many other sources of randmness that ISE might tap into. inode numbers, network traffic etc.
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<mithro>
rjo: their diffoscope tool might also help figure out where ISE starts to diverge (probably everywhere, but it would be good to find out) - that is how I tracked down the migen/misoc generating different verilog problem the first time
<rjo>
it also feels wrong to try to work around randomness in a huge hunk of commercial and closed software.
<larsc>
can't you set the seed value which should always result in the same bitstream?
<rjo>
memory addresses are another source of randomness.
<mithro>
larsc: That would be the case if the system was written by sane people
<mithro>
larsc: I've yet to see anything sane about ISE :-P
<sb0>
rjo, the TSP filament made quite a mess in my quick and dirty test. how do you prevent coating windows, electrical feedthroughs, etc. with titanium?
<sb0>
just baffles? or do you also have to be careful not to run the TSP too long/intensely?
<rjo>
;) deliberate placement of the tsp and/or shields.
<rjo>
it will just empty earlier. unless you also overheat stuff (feedthrough, faster gasket corrosion etc).
<mithro>
rjo: Anyway, bed time for me. If you discover anything, please do keep me informed.
<mithro>
Gnight!
<rjo>
and if you empty an entire filament, you get also titanium flaking of the walls. might be reactive if you vent.
<rjo>
mithro: good night.
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<sb0>
rjo, so does it meet timing fine at 75MHz now?
<sb0>
rjo, yes. i cranked it up enough for that (there is a vacuum chamber dedicated to messy/silly experiments). didn't notice anything happening when venting, though...
<sb0>
the pumping effect is nice
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<rjo>
yep. you should still bake though.
<rjo>
sb0: it consistently meets timing at 75 MHz so far. the tricky path is always long net delays in the cpu.